2023W

• Advanced Digital Design / 182.754 / LU
• Advanced Digital Design / 182.755 / VU
• Advanced FPGA Design / 182.756 / VU
• Bachelor Thesis for Computer Science and Business Informatics / 182.698 / PR
• Computer Engineering Practical / 191.005 / PR
• Computer Engineering Project / 191.006 / PR
• Computer Organization and Design / 182.690 / VO
• Current Trends in Computer Science / 195.072 / VU
• Democracy in the Digital Era / 199.015 / VU
• Digital Design / 182.693 / VO
• Doctorand's seminar / 182.070 / SE
• Epistemic Logic and Communication / 185.A98 / VU
• From surviving to thriving: crafting your good professional life / 199.096 / VU
• HW/SW Codesign / 182.701 / LU
• HW/SW Codesign / 182.700 / VU
• Orientation Bachelor with Honors of Informatics and Business Informatics / 180.767 / SE
• Philosophy of Science / 195.080 / VU
• Problems in Distributed Computing / 182.703 / VU
• Program Analysis / 199.014 / VU
• Project in Computer Science 1 / 191.008 / PR
• Project in Computer Science 2 / 191.009 / PR
• Propädeutikum für Informatik / 180.771 / VU
• Research Seminar LogiCS / 184.767 / SE
• Scientific Project Computer Engineering / 191.007 / PR
• Scientific Research and Writing / 193.052 / SE
• Seminar Computer Engineering / 182.757 / SE
• Seminar for Master Students in Computer Engineering / 180.778 / SE

2024S

• Introduction to Logical Methods in Computer Science / 184.766 / VO
• Research Seminar LogiCS / 184.767 / SE

• Trustworthy Autonomous Cyber-Physical Systems
  2023 – 2028 / TTTech Auto AG
• Reasoning about Knowledge in Byzantine Distributed Systems
  2020 – 2025 / Austrian Science Fund (FWF)
  Publication: 189852
• Robust Atomic Computing Platform and Enhanced Fault-Tolerant Distributed Algorithms 2
  2019 – 2024 / Intel Corporation
• Digital Modeling of Asynchronous Integrated Circuits
  2019 – 2024 / Austrian Science Fund (FWF)
  Publications: 135842 / 139754 / 189553 / 18019 / 18634
• Trustworthy IoT for CPS
  2017 – 2020 / Austrian Research Promotion Agency (FFG)
  Publication: 137649
• Robust Atomic Computing Platform and Enhanced Fault-Tolerant Distributed Algorithms
  2017 – 2019 / Intel Corporation
  Publications: 57708 / 57976 / 58042
• Gracefully Degrading Agreement in Directed Dynamic Networks
  2016 – 2020 / Austrian Science Fund (FWF)
  Publication: 18019
• Analysis & Modeling of Single-Event-Transients in VLSI Chips
  2014 – 2017 / Austrian Science Fund (FWF)
  Publications: 55859 / 55882 / 56884 / 56885

2023

• Extensions of K5: Proof Theory and Uniform Lyndon Interpolation / van der Giessen, I., Jalali, R., & Kuznets, R. (2023). Extensions of K5: Proof Theory and Uniform Lyndon Interpolation. In D. R. S. Ramanayake & J. Urban (Eds.), Automated Reasoning with Analytic Tableaux and Related Methods: 32nd International Conference, TABLEAUX 2023, Prague, Czech Republic, September 18–21, 2023, Proceedings (pp. 263–282). Springer. https://doi.org/10.1007/978-3-031-43513-3_15
  Download: publisher pdf (468 KB)
  Project: ByzDEL (2020–2025)
• A Sufficient Condition for Gaining Belief in Byzantine Fault-Tolerant Distributed Systems / Schlögl, T., & Schmid, U. (2023). A Sufficient Condition for Gaining Belief in Byzantine Fault-Tolerant Distributed Systems. In R. Verbrugge (Ed.), Proceedings Nineteenth conference on Theoretical Aspects of Rationality and Knowledge (pp. 487–506). https://doi.org/10.4204/EPTCS.379.37
  Project: DMAC (2019–2024)
• SeVuc: A study on the Security Vulnerabilities of Capsule Networks against adversarial attacks / Marchisio, A., Nanfa, G., Khalid, F., Hanif, M. A., Martina, M., & Shafique, M. (2023). SeVuc: A study on the Security Vulnerabilities of Capsule Networks against adversarial attacks. Microprocessors and Microsystems, 96, Article 104738. https://doi.org/10.1016/j.micpro.2022.104738

2022

• ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons / Prabakaran, B. S., Fasching, F., Schreib, J., Steininger, A., & Shafique, M. (2022). ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons. arXiv. https://doi.org/10.34726/3642
  Download: PDF (2.02 MB)
• LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor / Viale, A., Marchisio, A., Martina, M., Masera, G., & Shafique, M. (2022). LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor. In Proceedings 2022 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS) (pp. 79–86). https://doi.org/10.1109/IROS47612.2022.9981034
• Nested Sequents, Kripke Models, and Uniform Interpolation / van der Giessen, I., Jalali, R., & Kuznets, R. (2022, November 1). Nested Sequents, Kripke Models, and Uniform Interpolation [Conference Presentation]. Proof-theoretic and algebraic aspects of (intuitionistic) modal logics, Utrecht, Netherlands (the).
• An Accurate Hybrid Delay Model for Multi-Input Gates / Ferdowsi, A., Schmid, U., & Salzmann, J. (2022). An Accurate Hybrid Delay Model for Multi-Input Gates. https://doi.org/10.34726/2942
  Download: PDF (1.62 MB)
  Project: DMAC (2019–2024)
• Towards a Topological Semantics for Epistemic Reasoning in Byzantine Fault-Tolerant Distributed Systems / Randrianomentsoa, R. F., Rincon Galeana, H., & Schmid, U. (2022, October 24). Towards a Topological Semantics for Epistemic Reasoning in Byzantine Fault-Tolerant Distributed Systems [Conference Presentation]. Workshop on Connections between Epistemic Logic and Topology (CELT’22), University of Amsterdam, Netherlands (the). http://hdl.handle.net/20.500.12708/153197
• Study and Comparison of QDI Pipeline Components' Sensitivity to Permanent Faults / Elshehaby, R., & Steininger, A. (2022). Study and Comparison of QDI Pipeline Components’ Sensitivity to Permanent Faults. In IEEE (Ed.), 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE. https://doi.org/10.34726/4047
  Download: PDF (381 KB)
• SET Hardened Derivatives of QDI Buffer Template / Tabassam, Z., & Steininger, A. (2022). SET Hardened Derivatives of QDI Buffer Template. In IEEE (Ed.), 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE. https://doi.org/10.34726/3944
  Download: PDF (467 KB)
• RoHNAS: A Neural Architecture Search Framework With Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks / Marchisio, A., Mrazek, V., Massa, A., Bussolino, B., Martina, M., & Shafique, M. (2022). RoHNAS: A Neural Architecture Search Framework With Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks. IEEE Access, 10, 109043–109055. https://doi.org/10.1109/ACCESS.2022.3214312
• Framing faultiness Kripke style / van Ditmarsch, H., Fruzsa, K., & Kuznets, R. (2022, September 6). Framing faultiness Kripke style [Conference Presentation]. MOSAIC: Modalities in Substructural Logics: Theory, Methods and Applications, Kick Off Conference, Capaccio Paestum, Italy.
  Download: PDF (309 KB)
• Towards Resilient QDI Pipeline Implementations / Tabassam, Z., & Steininger, A. (2022). Towards Resilient QDI Pipeline Implementations. In IEEE (Ed.), 2022 25th Euromicro Conference on Digital System Design (DSD) (pp. 657–664). https://doi.org/10.34726/3942
  Download: PDF (597 KB)
• RIPEMB: A framework for assessing hardware-assisted software security schemes in embedded systems / Tauner, S. (2022). RIPEMB: A framework for assessing hardware-assisted software security schemes in embedded systems. In ARES ’22: Proceedings of the 17th International Conference on Availability, Reliability and Security (pp. 1–6). Association for Computing Machinery (ACM). https://doi.org/10.1145/3538969.3539013
  Download: PDF (608 KB)
• Hardware and Software Architectures for Energy-Efficient Smart Healthcare Systems / Prabakaran, B. S. (2022, July). Hardware and Software Architectures for Energy-Efficient Smart Healthcare Systems [Poster Presentation]. 2022 Design Automation Conference, United States of America (the). http://hdl.handle.net/20.500.12708/152496
• AμFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages / Tabassam, Z., Naqvi, S. R., & Steininger, A. (2022). AμFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (pp. 32–37). IEEE. https://doi.org/10.34726/3941
  Download: PDF (435 KB)
• TSCDA: a dynamic two-stage community discovery approach / Ferdowsi, A., Dehghan Chenary, M., & Khanteymoori, A. (2022). TSCDA: a dynamic two-stage community discovery approach. Social Network Analysis and Mining, 12, Article 46. https://doi.org/10.1007/s13278-022-00874-z
• A Tribute to Philosophical A Priori Knowledge Research in the Design and Analysis of Fault-Tolerant Distributed Systems / Cignarale, G. (2022, January 18). A Tribute to Philosophical A Priori Knowledge Research in the Design and Analysis of Fault-Tolerant Distributed Systems [Conference Presentation]. Meeting Eight Ticamore, Wien, Austria. http://hdl.handle.net/20.500.12708/153250
• A new hope / van Ditmarsch, H., Fruzsa, K., & Kuznets, R. (2022). A new hope. In D. Fernández-Duque, A. PALMIGIANO, & S. Pinchinat (Eds.), Advances in Modal Logic, Volume 14 (pp. 349–369). College Publications. https://doi.org/10.34726/2821
  Download: publisher pdf (869 KB)
• A Simple Hybrid Model for Accurate Delay Modeling of a Multi-Input Gate / Ferdowsi, A., Maier, J., Öhlinger, D., & Schmid, U. (2022). A Simple Hybrid Model for Accurate Delay Modeling of a Multi-Input Gate. In 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1461–1466). https://doi.org/10.23919/DATE54114.2022.9774547
  Project: DMAC (2019–2024)
• Architectures for Multimedia Processing: A Cross-Layer Perspective / Shafique, M., & Prabakaran, B. S. (2022). Architectures for Multimedia Processing: A Cross-Layer Perspective. In A. Chattopadhyay (Ed.), Handbook of Computer Architecture (pp. 1–22). Springer. https://doi.org/10.1007/978-981-15-6401-7_7-1
• A formal approach to identifying the impact of noise on neural networks / Bhatti, I. T., Naseer, M., Shafique, M., & Hasan, O. (2022). A formal approach to identifying the impact of noise on neural networks. Communications of the ACM, 65(11), 70–73. https://doi.org/10.1145/3550492
• lpSpikeCon: Enabling Low-Precision Spiking Neural Network Processing for Efficient Unsupervised Continual Learning on Autonomous Agents / Wicaksana Putra, R. V., & Shafique, M. (2022). lpSpikeCon: Enabling Low-Precision Spiking Neural Network Processing for Efficient Unsupervised Continual Learning on Autonomous Agents. In Proceedings 2022 International Joint Conference on Neural Networks (IJCNN) (pp. 1–8). https://doi.org/10.1109/IJCNN55064.2022.9892948
• fakeWeather: Adversarial Attacks for Deep Neural Networks Emulating Weather Conditions on the Camera Lens of Autonomous Systems / Marchisio, A., Caramia, G., Martina, M., & Shafique, M. (2022). fakeWeather: Adversarial Attacks for Deep Neural Networks Emulating Weather Conditions on the Camera Lens of Autonomous Systems. In Proceedings 2022 International Joint Conference on Neural Networks (IJCNN) (pp. 1–9). https://doi.org/10.1109/IJCNN55064.2022.9892612
• CoNLoCNN: Exploiting Correlation and Non-Uniform Quantization for Energy-Efficient Low-precision Deep Convolutional Neural Networks / Hanif, M. A., Sarda, G. M., Marchisio, A., Masera, G., Martina, M., & Shafique, M. (2022). CoNLoCNN: Exploiting Correlation and Non-Uniform Quantization for Energy-Efficient Low-precision Deep Convolutional Neural Networks. In 2Proceedings 2022 International Joint Conference on Neural Networks (IJCNN) (pp. 1–8). https://doi.org/10.1109/IJCNN55064.2022.9892902
• Continuous Tasks and the Asynchronous Computability Theorem / Galeana, H. R., Rajsbaum, S., & Schmid, U. (2022). Continuous Tasks and the Asynchronous Computability Theorem. In M. Braverman (Ed.), 13th Innovations in Theoretical Computer Science Conference (ITCS’22) (pp. 73:1-73:27). Schloss Dagstuhl - Leibniz-Zentrum für Informatik. https://doi.org/10.4230/LIPIcs.ITCS.2022.73
• Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems / Dave, S., Marchisio, A., Hanif, M. A., Guesmi, A., Shrivastava, A., Alouani, I., & Shafique, M. (2022). Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems. In Proceedings 2022 IEEE 40th VLSI Test Symposium (VTS) (pp. 1–14). https://doi.org/10.1109/VTS52500.2021.9794253
• Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations / Marchisio, A., Bussolino, B., Salvati, E., Martina, M., Masera, G., & Shafique, M. (2022). Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (pp. 1–6). https://doi.org/10.1145/3531437.3539717
• An Integer Programming Approach Reinforced by a Message-passing Procedure for Detecting Dense Attributed Subgraphs / Ferdowsi, A. (2022). An Integer Programming Approach Reinforced by a Message-passing Procedure for Detecting Dense Attributed Subgraphs. In M. Ganzha, L. Maciaszek, M. Paprzycki, & D. Ślęzak (Eds.), Proceedings of the 17th Conference on Computer Science and Intelligence Systems (pp. 569–576). https://doi.org/10.15439/2022F64
• SoftSNN: Low-Cost Fault Tolerance for Spiking Neural Network Accelerators under Soft Errors / Putra, R. V. W., Hanif, M. A., & Shafique, M. (2022). SoftSNN: Low-Cost Fault Tolerance for Spiking Neural Network Accelerators under Soft Errors. In DAC ’22: Proceedings of the 59th ACM/IEEE Design Automation Conference (pp. 151–156). https://doi.org/10.1145/3489517.3530657
• EnforceSNN: Enabling resilient and energy-efficient spiking neural network inference considering approximate DRAMs for embedded systems / Putra, R. V. W., Hanif, M. A., & Shafique, M. (2022). EnforceSNN: Enabling resilient and energy-efficient spiking neural network inference considering approximate DRAMs for embedded systems. Frontiers in Neuroscience, 16. https://doi.org/10.3389/fnins.2022.937782
• NeuroUnlock: Unlocking the Architecture of Obfuscated Deep Neural Networks / Ahmadi, M. M., Alrahis, L., Colucci, A., Sinanoglu, O., & Shafique, M. (2022). NeuroUnlock: Unlocking the Architecture of Obfuscated Deep Neural Networks. In Proceedings 2022 International Joint Conference on Neural Networks (IJCNN) (pp. 01–10). https://doi.org/10.1109/IJCNN55064.2022.9892545
• AccelAT: A Framework for Accelerating the Adversarial Training of Deep Neural Networks Through Accuracy Gradient / Nikfam, F., Marchisio, A., Martina, M., & Shafique, M. (2022). AccelAT: A Framework for Accelerating the Adversarial Training of Deep Neural Networks Through Accuracy Gradient. IEEE Access, 10, 108997–109007. https://doi.org/10.1109/ACCESS.2022.3213734
• enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks / Colucci, A., Steininger, A., & Shafique, M. (2022). enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks. In Proceedings 2022 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS) (pp. 5155–5162). https://doi.org/10.1109/IROS47612.2022.9982181

2021

• Gain and Pain of a Reliable Delay Model / Maier, J. (2021). Gain and Pain of a Reliable Delay Model. In Proceedings 2021 24th Euromicro Conference on Digital System Design DSD 2021 (pp. 246–250). https://doi.org/10.34726/1681
  Download: PDF (345 KB)
  Project: DMAC (2019–2024)
• Justification logic for constructive modal logic / Kuznets, R., Marin, S., & Straßburger, L. (2021). Justification logic for constructive modal logic. Journal of Applied Logics, 8(8), 2313–2332. https://doi.org/10.34726/2943
  Download: publisher pdf (506 KB)
  Projects: LOGFRADIG (2013–2017) / NestSIRea (2015–2017) / ZK 35-G (2019–2024)
• A Composable Glitch-Aware Delay Model / Maier, J., Öhlinger, D., Schmid, U., Függer, M., & Nowak, T. (2021). A Composable Glitch-Aware Delay Model. In GLSVLSI ’21: Proceedings of the 2021 Great Lakes Symposium on VLSI (pp. 147–154). Association for Computing Machinery. https://doi.org/10.1145/3453688.3461519
  Downloads: MP4 (85.5 MB) / PDF (1.28 MB)
  Projects: ADynNet (2016–2020) / DMAC (2019–2024)
• Generation of a fault-tolerant clock through redundant crystal oscillators / Dür, W., Függer, M., & Steininger, A. (2021). Generation of a fault-tolerant clock through redundant crystal oscillators. Microelectronics Reliability, 120, 1–11. https://doi.org/10.1016/j.microrel.2021.114088
  Download: PDF (1.46 MB)
• Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles / Behal, P., Huemer, F., Najvirt, R., Tabassam, Z., & Steininger, A. (2021). Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. In 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 27th IEEE International Symposium on Asynchronous Circuits and Systems, online, Austria. https://doi.org/10.34726/3945
  Download: PDF (717 KB)
• Input/Output-Interlocking for Fault Mitigation in QDI Pipelines / Tabassam, Z., Behal, P., Najvirt, R., & Steininger, A. (2021). Input/Output-Interlocking for Fault Mitigation in QDI Pipelines. In 2021 Austrochip Workshop on Microelectronics (Austrochip) (pp. 17–20). https://doi.org/10.34726/3943
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• Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines / Elshehaby, R., & Steininger, A. (2021). Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Wien, Austria. Ieee Cs. https://doi.org/10.34726/4046
  Download: PDF (497 KB)
• An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits / Behal, P., Huemer, F. F., Najvirt, R., & Steininger, A. (2021). An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. In 2021 24th Euromicro Conference on Digital System Design (DSD). 24th Euromicro Conference on Digital System Design, Palermo, Italy, EU. https://doi.org/10.34726/4044
  Download: PDF (506 KB)
• Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles / Behal, P., Huemer, F., Najvirt, R., Steininger, A., & Tabassam, Z. (2021). Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). https://doi.org/10.1109/async48570.2021.00012
• Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses / Maier, J., Hartl-Nesic, C., & Steininger, A. (2021). Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(3), 1013–1026. https://doi.org/10.1109/tcsi.2021.3130349
• GNNUnlock+: A Systematic Methodology for Designing Graph Neural Networks-based Oracle-less Unlocking Schemes for Provably Secure Logic Locking / Alrahis, L., Patnaik, S., Hanif, M. A., Saleh, H., Shafique, M., & Sinanoglu, O. (2021). GNNUnlock+: A Systematic Methodology for Designing Graph Neural Networks-based Oracle-less Unlocking Schemes for Provably Secure Logic Locking. IEEE Transactions on Emerging Topics in Computing, 10(3), 1575–1592. https://doi.org/10.1109/tetc.2021.3108487
• A survey of hardware architectures for generative adversarial networks / Shrivastava, N., Hanif, M. A., Mittal, S., Sarangi, S. R., & Shafique, M. (2021). A survey of hardware architectures for generative adversarial networks. The Journal of Systems Architecture: Embedded Software Design, 118(102227), 102227. https://doi.org/10.1016/j.sysarc.2021.102227
• Generation of a fault-tolerant clock through redundant crystal oscillators / Dür, W., Függer, M., & Steininger, A. (2021). Generation of a fault-tolerant clock through redundant crystal oscillators. Microelectronics Reliability, 120(114088), 114088. https://doi.org/10.1016/j.microrel.2021.114088
• Interpolation for intermediate logics via injective nested sequents / Kuznets, R., & Lellmann, B. (2021). Interpolation for intermediate logics via injective nested sequents. Journal of Logic and Computation, 31(3), 797–831. https://doi.org/10.1093/logcom/exab015
• FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators / Marchisio, A., Mrazek, V., Hanif, M. A., & Shafique, M. (2021). FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29(4), 716–729. https://doi.org/10.1109/tvlsi.2021.3059518
• ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators / Putra, R. V. W., Hanif, M. A., & Shafique, M. (2021). ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29(4), 702–715. https://doi.org/10.1109/tvlsi.2021.3060509
• BioNetExplorer: Architecture-Space Exploration of Biosignal Processing Deep Neural Networks for Wearables / Prabakaran, B. S., Akhtar, A., Rehman, S., Hasan, O., & Shafique, M. (2021). BioNetExplorer: Architecture-Space Exploration of Biosignal Processing Deep Neural Networks for Wearables. IEEE Internet of Things Journal, 8(17), 13251–13265. https://doi.org/10.1109/jiot.2021.3065815
• TiQSA: Workload Minimization in Convolutional Neural Networks Using Tile Quantization and Symmetry Approximation / Sabir, D., Hanif, M. A., Hassan, A., Rehman, S., & Shafique, M. (2021). TiQSA: Workload Minimization in Convolutional Neural Networks Using Tile Quantization and Symmetry Approximation. IEEE Access, 9, 53647–53668. https://doi.org/10.1109/access.2021.3069906
• FeSHI: Feature Map-Based Stealthy Hardware Intrinsic Attack / Odetola, T. A., Khalid, F., Mohammed, H., Sandefur, T. C., & Hasan, S. R. (2021). FeSHI: Feature Map-Based Stealthy Hardware Intrinsic Attack. IEEE Access, 9, 115370–115387. https://doi.org/10.1109/access.2021.3104520
• Weight Quantization Retraining for Sparse and Compressed Spatial Domain Correlation Filters / Sabir, D., Hanif, M. A., Hassan, A., Rehman, S., & Shafique, M. (2021). Weight Quantization Retraining for Sparse and Compressed Spatial Domain Correlation Filters. Electronics, 10(3), 351. https://doi.org/10.3390/electronics10030351
• Optimal strategies for selecting coordinators / Zeiner, M., Schmid, U., & Chatterjee, K. (2021). Optimal strategies for selecting coordinators. Discrete Applied Mathematics, 289, 392–415. https://doi.org/10.1016/j.dam.2020.10.022
• Hardware-Assisted Control Flow Integrity Schemes on RISC-V / Tauner, S., Telesklav, M., & Halder, L. (2021). Hardware-Assisted Control Flow Integrity Schemes on RISC-V. Second International Workshop on Secure RISC-V (SECRISC-V), Virtual, International. http://hdl.handle.net/20.500.12708/87276
• Honors at TU Wien / Schmid, U. (2021). Honors at TU Wien. International Conference on Talent Development and Honors Education (World of Talent 2021), Groningen, The Netherlands, International. http://hdl.handle.net/20.500.12708/87249
• Intuiting Duals of Proofs / Kuznets, R., Marin, S., & Strassburger, L. (2021). Intuiting Duals of Proofs. Milano Logic Group Logic Lunch Seminar Series, online, Italy, International. http://hdl.handle.net/20.500.12708/87263
• Q-SpiNN: A Framework for Quantizing Spiking Neural Networks / Putra, R. V. W., & Shafique, M. (2021). Q-SpiNN: A Framework for Quantizing Spiking Neural Networks. In 2021 International Joint Conference on Neural Networks (IJCNN). 2021 International Joint Conference on Neural Networks, Virtual Conference, International. https://doi.org/10.1109/ijcnn52387.2021.9534087
• ReSpawn: Energy-Efficient Fault-Tolerance for Spiking Neural Networks considering Unreliable Memories / Wicaksana Putra, R. V., Hanif, M. A., & Shafique, M. (2021). ReSpawn: Energy-Efficient Fault-Tolerance for Spiking Neural Networks considering Unreliable Memories. In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). 2021 International Conference On Computer-Aided Design, Virtual Conference, International. https://doi.org/10.1109/iccad51958.2021.9643524
• SpikeDyn: A Framework for Energy-Efficient Spiking Neural Networks with Continual and Unsupervised Learning Capabilities in Dynamic Environments / Putra, R. V. W., & Shafique, M. (2021). SpikeDyn: A Framework for Energy-Efficient Spiking Neural Networks with Continual and Unsupervised Learning Capabilities in Dynamic Environments. In 2021 58th ACM/IEEE Design Automation Conference (DAC). 2021 58th ACM/IEEE Design Automation Conference (DAC), San Francisco, California, USA, International. https://doi.org/10.1109/dac18074.2021.9586281
• SparkXD: A Framework for Resilient and Energy-Efficient Spiking Neural Network Inference using Approximate DRAM / Putra, R. V. W., Hanif, M. A., & Shafique, M. (2021). SparkXD: A Framework for Resilient and Energy-Efficient Spiking Neural Network Inference using Approximate DRAM. In 2021 58th ACM/IEEE Design Automation Conference (DAC). 2021 58th ACM/IEEE Design Automation Conference (DAC), San Francisco, California, USA, International. https://doi.org/10.1109/dac18074.2021.9586332
• Security Analysis of Capsule Network Inference using Horizontal Collaboration / Adeyemo, A., Khalid, F., Odetola, T., & Hasan, S. R. (2021). Security Analysis of Capsule Network Inference using Horizontal Collaboration. In 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Virtual Conference, International. https://doi.org/10.1109/mwscas47672.2021.9531833
• R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors / Marchisio, A., Pira, G., Martina, M., Masera, G., & Shafique, M. (2021). R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors. In 2021 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS). 2021 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), Virtual Conference, International. https://doi.org/10.1109/iros51168.2021.9636718
• CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor / Viale, A., Marchisio, A., Martina, M., Masera, G., & Shafique, M. (2021). CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor. In 2021 International Joint Conference on Neural Networks (IJCNN). 2021 International Joint Conference on Neural Networks, Virtual Conference, International. https://doi.org/10.1109/ijcnn52387.2021.9533738
• DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks / Marchisio, A., Pira, G., Martina, M., Masera, G., & Shafique, M. (2021). DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks. In 2021 International Joint Conference on Neural Networks (IJCNN). 2021 International Joint Conference on Neural Networks, Virtual Conference, International. https://doi.org/10.1109/ijcnn52387.2021.9534364
• Towards Energy-Efficient and Secure Edge AI: A Cross-Layer Framework ICCAD Special Session Paper / Shafique, M., Marchisio, A., Wicaksana Putra, R. V., & Hanif, M. A. (2021). Towards Energy-Efficient and Secure Edge AI: A Cross-Layer Framework ICCAD Special Session Paper. In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). 2021 International Conference On Computer-Aided Design, Virtual Conference, International. https://doi.org/10.1109/iccad51958.2021.9643539
• Securing Deep Spiking Neural Networks against Adversarial Attacks through Inherent Structural Parameters / El-Allami, R., Marchisio, A., Shafique, M., & Alouani, I. (2021). Securing Deep Spiking Neural Networks against Adversarial Attacks through Inherent Structural Parameters. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2021 Design, Automation & Test in Europe, Online, International. https://doi.org/10.23919/date51398.2021.9473981
• UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction / Alrahis, L., Patnaik, S., Hanif, M. A., Shafique, M., & Sinanoglu, O. (2021). UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction. In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). 2021 International Conference On Computer-Aided Design, Virtual Conference, International. https://doi.org/10.1109/iccad51958.2021.9643476
• Emerging Computing Devices: Challenges and Opportunities for Test and Reliability / Bosio, A., O´Connor, I., Traiola, M., Echavarria, J., Teich, J., Hanif, M. A., Shafique, M., Hamdioui, S., Deveautour, B., Girard, P., & Bertels, K. (2021). Emerging Computing Devices: Challenges and Opportunities for Test and Reliability. In 2021 IEEE European Test Symposium (ETS). 2021 IEEE European Test Symposium (ETS), Virtual Conference, International. https://doi.org/10.1109/ets50041.2021.9465409
• TRe-Map: Towards Reducing the Overheads of Fault-Aware Retraining of Deep Neural Networks by Merging Fault Maps / Hoang, L.-H., Hanif, M. A., & Shafique, M. (2021). TRe-Map: Towards Reducing the Overheads of Fault-Aware Retraining of Deep Neural Networks by Merging Fault Maps. In 2021 24th Euromicro Conference on Digital System Design (DSD). 2021 24th Euromicro Conference on Digital System Design, Virtual Conference, International. https://doi.org/10.1109/dsd53832.2021.00072
• DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures / Hanif, M. A., & Shafique, M. (2021). DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2021 Design, Automation & Test in Europe, Online, International. https://doi.org/10.23919/date51398.2021.9473943
• GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking / Alrahis, L., Patnaik, S., Khalid, F., Hanif, M. A., Saleh, H., Shafique, M., & Sinanoglu, O. (2021). GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2021 Design, Automation & Test in Europe, Online, International. https://doi.org/10.23919/date51398.2021.9474039
• Uniform Interpolation via Nested Sequents / van der Giessen, I., Jalali, R., & Kuznets, R. (2021). Uniform Interpolation via Nested Sequents. In Logic, Language, Information, and Computation (pp. 337–354). Lecture Notes in Computer Science. https://doi.org/10.1007/978-3-030-88853-4_21
• Fire! / Fruzsa, K., Kuznets, R., & Schmid, U. (2021). Fire! In Electronic Proceedings in Theoretical Computer Science (pp. 139–153). Electronic Proceedings in Theoretical Computer Science. https://doi.org/10.4204/eptcs.335.13
• Valency-Based Consensus Under Message Adversaries Without Limit-Closure / Winkler, K., Schmid, U., & Nowak, T. (2021). Valency-Based Consensus Under Message Adversaries Without Limit-Closure. In Fundamentals of Computation Theory (pp. 457–474). Springer. https://doi.org/10.1007/978-3-030-86593-1_32
• Round-Oblivious Stabilizing Consensus in Dynamic Networks / Schwarz, M., & Schmid, U. (2021). Round-Oblivious Stabilizing Consensus in Dynamic Networks. In Lecture Notes in Computer Science (pp. 154–172). Springer. https://doi.org/10.1007/978-3-030-91081-5_11
• MLComp: A Methodology for Machine Learning-based Performance Estimation and Adaptive Selection of Pareto-Optimal Compiler Optimization Sequences / Colucci, A., Juhasz, D., Mosbeck, M., Marchisio, A., Rehman, S., Kreutzer, M., Nadbath, G., Jantsch, A., & Shafique, M. (2021). MLComp: A Methodology for Machine Learning-based Performance Estimation and Adaptive Selection of Pareto-Optimal Compiler Optimization Sequences. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2021 Design, Automation & Test in Europe, Online, International. https://doi.org/10.23919/date51398.2021.9474158
• Foreword / Sekanina, L., Shafique, M., Krstic, M., Steininger, A., & Stojanovic, G. (2021). Foreword. In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE. https://doi.org/10.1109/ddecs52668.2021.9417019
• Automated HW/SW co-design for edge AI / Bringmann, O., Ecker, W., Feldner, I., Frischknecht, A., Gerum, C., Hämäläinen, T., Hanif, M. A., Klaiber, M., Mueller-Gritschneder, D., Prebeck, S., & Shafique, M. (2021). Automated HW/SW co-design for edge AI. In Proceedings of the 2021 International Conference on Hardware/Software Codesign and System Synthesis. 2021 International Conference on Hardware/Software Codesign and System Synthesis, Virtual Conference, International. Association for Computing Machinery, New York, NY, United States. https://doi.org/10.1145/3478684.3479261
• Comparative Analysis and Enhancement of CFG-based Hardware-Assisted CFI Schemes / Tauner, S., & Telesklav, M. (2021). Comparative Analysis and Enhancement of CFG-based Hardware-Assisted CFI Schemes. In ACM Transactions on Embedded Computing Systems (pp. 1–25). Association for Computing Machinery. https://doi.org/10.1145/3476989
• Uniform interpolation via nested sequents and hypersequents / van der Giessen, I., Jalali, R., & Kuznets, R. (2021). Uniform interpolation via nested sequents and hypersequents (2105.10930). http://hdl.handle.net/20.500.12708/40454

2020

• Guest Editors' Introduction: Robust Resource-Constrained Machine Learning / Theocharides, T., Shafique, M., Choi, J., & Mutlu, O. (2020). Guest Editors’ Introduction: Robust Resource-Constrained Machine Learning. IEEE Design and Test, 37(2), 5–7. https://doi.org/10.1109/mdat.2020.2971201
• A Multi-Agent Depth Bounded Boolean Logic / Cignarale, G., & Primiero, G. (2020). A Multi-Agent Depth Bounded Boolean Logic. In Software Engineering and Formal Methods. SEFM 2020 Collocated Workshops (pp. 176–191). https://doi.org/10.1007/978-3-030-67220-1_14
• A Faithful Binary Circuit Model / Függer, M., Najvirt, R., Nowak, T., & Schmid, U. (2020). A Faithful Binary Circuit Model. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(10), 2784–2797. https://doi.org/10.1109/tcad.2019.2937748
• SSCNets: Robustifying DNNs using Secure Selective Convolutional Filters / Ali, H., Khalid, F., Tariq, H. A., Hanif, M. A., Ahmed, R., & Rehman, S. (2020). SSCNets: Robustifying DNNs using Secure Selective Convolutional Filters. IEEE Design and Test, 37(2), 58–65. https://doi.org/10.1109/mdat.2019.2961325
• Robust Computing for Machine Learning-Based Systems / Hanif, M. A., Khalid, F., Putra, R. V. W., Teimoori, M. T., Kriebel, F., Zhang, J. (Jun), Liu, K., Rehman, S., Theocharides, T., Artusi, A., Garg, S., & Shafique, M. (2020). Robust Computing for Machine Learning-Based Systems. In J. Henkel & N. Dutt (Eds.), Dependable Embedded Systems (pp. 479–503). Springer Nature Switzerland AG. https://doi.org/10.1007/978-3-030-52017-5_20
• Identification and Confinement of Fault Sensitivity Windows in QDI Logic / Huemer, F. F., Najvirt, R., & Steininger, A. (2020). Identification and Confinement of Fault Sensitivity Windows in QDI Logic. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. https://doi.org/10.34726/4043
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• Timing Domain Crossing using Muller Pipelines / Huemer, F. F., & Steininger, A. (2020). Timing Domain Crossing using Muller Pipelines. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 26th IEEE International Symposium on Asynchronous Circuits and Systems, Snowbird, Utah, USA, Austria. Ieee Cs. https://doi.org/10.34726/4041
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• On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective / Elshehaby, R., & Steininger, A. (2020). On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. In 2020 IEEE 38th International Conference on Computer Design (ICCD). IEEE International Conference on Computer Design, Hartford, Connecticut, USA, Austria. https://doi.org/10.34726/4045
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• Sorting Network based Full Adders for QDI Circuits / Huemer, F. F., & Steininger, A. (2020). Sorting Network based Full Adders for QDI Circuits. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. https://doi.org/10.34726/4042
  Download: PDF (280 KB)
• SIMCom: Statistical Sniffing of Inter-Module Communications for Runtime Hardware Trojan Detection / Khalid, F., Hasan, S. R., Hasan, O., & Shafique, M. (2020). SIMCom: Statistical Sniffing of Inter-Module Communications for Runtime Hardware Trojan Detection. Microprocessors and Microsystems, 77(103122), 103122. https://doi.org/10.1016/j.micpro.2020.103122
• Upper and Lower Bounds for the Synchronizer Performance in Systems with Probabilistic Message Loss / Zeiner, M., & Schmid, U. (2020). Upper and Lower Bounds for the Synchronizer Performance in Systems with Probabilistic Message Loss. Methodology and Computing in Applied Probability, 23(3), 1023–1056. https://doi.org/10.1007/s11009-020-09792-z
• Combinatorial Auctions for Temperature-Constrained Resource Management in Manycores / Khdr, H., Shafique, M., Pagani, S., Herkersdorf, A., & Henkel, J. (2020). Combinatorial Auctions for Temperature-Constrained Resource Management in Manycores. IEEE Transactions on Parallel and Distributed Systems, 31(7), 1605–1620. https://doi.org/10.1109/tpds.2020.2965523
• Longevity Framework: Leveraging Online Integrated Aging-Aware Hierarchical Mapping and VF-Selection for Lifetime Reliability Optimization in Manycore Processors / Rathore, V., Chaturvedi, V., Singh, A. K., Srikanthan, T., & Shafique, M. (2020). Longevity Framework: Leveraging Online Integrated Aging-Aware Hierarchical Mapping and VF-Selection for Lifetime Reliability Optimization in Manycore Processors. IEEE Transactions on Computers, 70(7), 1106–1119. https://doi.org/10.1109/tc.2020.3006571
• Precedence-Aware Automated Competitive Analysis of Real-Time Scheduling / Pavlogiannis, A., Schaumberger, N., Schmid, U., & Chatterjee, K. (2020). Precedence-Aware Automated Competitive Analysis of Real-Time Scheduling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 3981–3992. https://doi.org/10.1109/tcad.2020.3012803
• SuperSlash: A Unified Design Space Exploration and Model Compression Methodology for Design of Deep Learning Accelerators With Reduced Off-Chip Memory Access Volume / Ahmad, H., Arif, T., Hanif, M. A., Hafiz, R., & Shafique, M. (2020). SuperSlash: A Unified Design Space Exploration and Model Compression Methodology for Design of Deep Learning Accelerators With Reduced Off-Chip Memory Access Volume. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 4191–4204. https://doi.org/10.1109/tcad.2020.3012865
• DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware / Marchisio, A., Mrazek, V., Hanif, M. A., & Shafique, M. (2020). DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40(9), 1768–1781. https://doi.org/10.1109/tcad.2020.3030610
• MacLeR: Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices / Khalid, F., Hasan, S. R., Zia, S., Hasan, O., Awwad, F., & Shafique, M. (2020). MacLeR: Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 3748–3761. https://doi.org/10.1109/tcad.2020.3012236
• FSpiNN: An Optimization Framework for Memory-Efficient and Energy-Efficient Spiking Neural Networks / Putra, R. V. W., & Shafique, M. (2020). FSpiNN: An Optimization Framework for Memory-Efficient and Energy-Efficient Spiking Neural Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 3601–3613. https://doi.org/10.1109/tcad.2020.3013049
• Robust Machine Learning Systems: Challenges,Current Trends, Perspectives, and the Road Ahead / Shafique, M., Naseer, M., Theocharides, T., Kyrkou, C., Mutlu, O., Orosa, L., & Choi, J. (2020). Robust Machine Learning Systems: Challenges,Current Trends, Perspectives, and the Road Ahead. IEEE Design and Test, 37(2), 30–57. https://doi.org/10.1109/mdat.2020.2971217
• Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead / Capra, M., Bussolino, B., Marchisio, A., Masera, G., Martina, M., & Shafique, M. (2020). Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead. IEEE Access, 8, 225134–225180. https://doi.org/10.1109/access.2020.3039858
• Probabilistic Analysis of Targeted Attacks Using Transform-Domain Adversarial Examples / Yahya, Z., Hassan, M., Younis, S., & Shafique, M. (2020). Probabilistic Analysis of Targeted Attacks Using Transform-Domain Adversarial Examples. IEEE Access, 8, 33855–33869. https://doi.org/10.1109/access.2020.2974525
• xUAVs: Towards Efficient Approximate Computing for UAVs-Low Power Approximate Adders With Single LUT Delay for FPGA-Based Aerial Imaging Optimization / Nomani, T., Mohsin, M., Pervaiz, Z., & Shafique, M. (2020). xUAVs: Towards Efficient Approximate Computing for UAVs-Low Power Approximate Adders With Single LUT Delay for FPGA-Based Aerial Imaging Optimization. IEEE Access, 8, 102982–102996. https://doi.org/10.1109/access.2020.2998957
• Peak-Power-Aware Primary-Backup Technique for Efficient Fault-Tolerance in Multicore Embedded Systems / Ansari, M., Salehi, M., Safari, S., Ejlali, A., & Shafique, M. (2020). Peak-Power-Aware Primary-Backup Technique for Efficient Fault-Tolerance in Multicore Embedded Systems. IEEE Access, 8, 142843–142857. https://doi.org/10.1109/access.2020.3013721
• Resistive Crossbar-Aware Neural Network Design and Optimization / Hanif, M. A., Manglik, A., & Shafique, M. (2020). Resistive Crossbar-Aware Neural Network Design and Optimization. IEEE Access, 8, 229066–229085. https://doi.org/10.1109/access.2020.3045071
• CAxCNN: Towards the Use of Canonic Sign Digit Based Approximation for Hardware-Friendly Convolutional Neural Networks / Riaz, M., Hafiz, R., Khaliq, S. A., Faisal, M., Iqbal, H. T., Ali, M., & Shafique, M. (2020). CAxCNN: Towards the Use of Canonic Sign Digit Based Approximation for Hardware-Friendly Convolutional Neural Networks. IEEE Access, 8, 127014–127021. https://doi.org/10.1109/access.2020.3008256
• APNAS: Accuracy-and-Performance-Aware Neural Architecture Search for Neural Hardware Accelerators / Achararit, P., Hanif, M. A., Putra, R. V. W., Shafique, M., & Hara-Azumi, Y. (2020). APNAS: Accuracy-and-Performance-Aware Neural Architecture Search for Neural Hardware Accelerators. IEEE Access, 8, 165319–165334. https://doi.org/10.1109/access.2020.3022327
• On the radius of nonsplit graphs and information dissemination in dynamic networks / Függer, M., Nowak, T., & Winkler, K. (2020). On the radius of nonsplit graphs and information dissemination in dynamic networks. Discrete Applied Mathematics, 282, 257–264. https://doi.org/10.1016/j.dam.2020.02.013
• PEAL: Probabilistic Error Analysis Methodology for Low-power Approximate Adders / Ayub, M. K., Hanif, M. A., Hasan, O., & Shafique, M. (2020). PEAL: Probabilistic Error Analysis Methodology for Low-power Approximate Adders. ACM Journal on Emerging Technologies in Computing Systems, 17(1), 1–37. https://doi.org/10.1145/3405430
• Efficient Loading And Visualization Of Massive Feature-Rich Point Clouds Without Hierarchical Acceleration Structures / Otepka, J., Mandlburger, G., Schütz, M., Pfeifer, N., & Wimmer, M. (2020). Efficient Loading And Visualization Of Massive Feature-Rich Point Clouds Without Hierarchical Acceleration Structures. The International Archives of the Photogrammetry, Remote Sensing and Spatial Information Sciences, XLIII-B2-2020, 293–300. https://doi.org/10.5194/isprs-archives-xliii-b2-2020-293-2020
• An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks / Capra, M., Bussolino, B., Marchisio, A., Shafique, M., Masera, G., & Martina, M. (2020). An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks. Future Internet, 12(7), 113. https://doi.org/10.3390/fi12070113
• Welcome Message: ASYNC 2020 / Brunvand, E., Stevens, K., Moreira, M., & Steininger, A. (2020). Welcome Message: ASYNC 2020. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE Computer Society. https://doi.org/10.1109/async49171.2020.00005
• Interpolation for Intermediate Logics via Injective Nested Sequents / Kuznets, R., & Lellmann, B. (2020). Interpolation for Intermediate Logics via Injective Nested Sequents. Online Partout Seminar, online, France, International. http://hdl.handle.net/20.500.12708/87072
• FaDec: A Fast Decision-based Attack for Adversarial Machine Learning / Khalid, F., Hassan, A., Hanif, M. A., Rehman, S., Ahmed, R., & Shafique, M. (2020). FaDec: A Fast Decision-based Attack for Adversarial Machine Learning. In 2020 International Joint Conference on Neural Networks (IJCNN). IJCNN. https://doi.org/10.1109/ijcnn48605.2020.9207635
• Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock / Duer, W., & Steininger, A. (2020). Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock. In 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Novi Sad, EU. Ieee Cs. https://doi.org/10.1109/ddecs50862.2020.9095577
• DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks / Wicaksana Putra, R. V., Abdullah Hanif, M., & Shafique, M. (2020). DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks. In 2020 57th ACM/IEEE Design Automation Conference (DAC). 2020 57th ACM/IEEE Design Automation Conference (DAC), San Fransisco, USA (Virtual), Non-EU. IEEE. https://doi.org/10.1109/dac18072.2020.9218672
• FANNet: Formal Analysis of Noise Tolerance, Training Bias and Input Sensitivity in Neural Networks / Naseer, M., Minhas, M. F., Khalid, F., Hanif, M. A., Hasan, O., & Shafique, M. (2020). FANNet: Formal Analysis of Noise Tolerance, Training Bias and Input Sensitivity in Neural Networks. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, EU. IEEE. https://doi.org/10.23919/date48585.2020.9116247
• FT-ClipAct: Resilience Analysis of Deep Neural Networks and Improving their Fault Tolerance using Clipped Activation / Hoang, L.-H., Hanif, M. A., & Shafique, M. (2020). FT-ClipAct: Resilience Analysis of Deep Neural Networks and Improving their Fault Tolerance using Clipped Activation. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, EU. IEEE. https://doi.org/10.23919/date48585.2020.9116571
• FaDec: A Fast Decision-based Attack for Adversarial Machine Learning / Khalid, F., Ali, H., Abdullah Hanif, M., Rehman, S., Ahmed, R., & Shafique, M. (2020). FaDec: A Fast Decision-based Attack for Adversarial Machine Learning. In 2020 International Joint Conference on Neural Networks (IJCNN). 2020 International Joint Conference on Neural Networks (IJCNN), Glasgow, UK, Non-EU. IEEE. https://doi.org/10.1109/ijcnn48605.2020.9207635
• AUGER: A Tool for Generating Approximate Arithmetic Circuits / Hernandez-Araya, D., Castro-Godinez, J., Shafique, M., & Henkel, J. (2020). AUGER: A Tool for Generating Approximate Arithmetic Circuits. In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), San Jose, Costa Rica, Non-EU. IEEE. https://doi.org/10.1109/lascas45839.2020.9069045
• Approximate Acceleration for CNN-based Applications on IoT Edge Devices / Castro-Godinez, J., Hernandez-Araya, D., Shafique, M., & Henkel, J. (2020). Approximate Acceleration for CNN-based Applications on IoT Edge Devices. In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), San Jose, Costa Rica, Non-EU. IEEE. https://doi.org/10.1109/lascas45839.2020.9069040
• Towards Quality-Driven Approximate Software Generation for Accurate Hardware: Work-in-Progress / Castro-Godinez, J., Shafique, M., & Henkel, J. (2020). Towards Quality-Driven Approximate Software Generation for Accurate Hardware: Work-in-Progress. In 2020 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES). 2020 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Virtual Conference, Austria. IEEE. https://doi.org/10.1109/cases51649.2020.9243814
• ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems / Prabakaran, B. S., Mrazek, V., Vasicek, Z., Sekanina, L., & Shafique, M. (2020). ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. In 2020 57th ACM/IEEE Design Automation Conference (DAC). 2020 57th ACM/IEEE Design Automation Conference (DAC), San Fransisco, USA (Virtual), Non-EU. IEEE. https://doi.org/10.1109/dac18072.2020.9218533
• EMAP: A Cloud-Edge Hybrid Framework for EEG Monitoring and Cross-Correlation Based Real-time Anomaly Prediction / Prabakaran, B. S., Garcia Jimenez, A., Martinez, G. M., & Shafique, M. (2020). EMAP: A Cloud-Edge Hybrid Framework for EEG Monitoring and Cross-Correlation Based Real-time Anomaly Prediction. In 2020 57th ACM/IEEE Design Automation Conference (DAC). 2020 57th ACM/IEEE Design Automation Conference (DAC), San Fransisco, USA (Virtual), Non-EU. IEEE. https://doi.org/10.1109/dac18072.2020.9218713
• A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress / Colucci, A., Marchisio, A., Bussolino, B., Mrazek, V., Martina, M., Masera, G., & Shafique, M. (2020). A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. In 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS), Virtual Conference, Austria. IEEE. https://doi.org/10.1109/codesisss51650.2020.9244038
• An Efficient Spiking Neural Network for Recognizing Gestures with a DVS Camera on the Loihi Neuromorphic Processor / Massa, R., Marchisio, A., Martina, M., & Shafique, M. (2020). An Efficient Spiking Neural Network for Recognizing Gestures with a DVS Camera on the Loihi Neuromorphic Processor. In 2020 International Joint Conference on Neural Networks (IJCNN). 2020 International Joint Conference on Neural Networks (IJCNN), Glasgow, UK, Non-EU. IEEE. https://doi.org/10.1109/ijcnn48605.2020.9207109
• NeuroAttack: Undermining Spiking Neural Networks Security through Externally Triggered Bit-Flips / Venceslai, V., Marchisio, A., Alouani, I., Martina, M., & Shafique, M. (2020). NeuroAttack: Undermining Spiking Neural Networks Security through Externally Triggered Bit-Flips. In 2020 International Joint Conference on Neural Networks (IJCNN). 2020 International Joint Conference on Neural Networks (IJCNN), Glasgow, UK, Non-EU. IEEE. https://doi.org/10.1109/ijcnn48605.2020.9207351
• The Persistence of False Memory: Brain in a Vat despite Perfect Clocks / Schlögl, T., Schmid, U., & Kuznets, R. (2020). The Persistence of False Memory: Brain in a Vat despite Perfect Clocks. In Lecture Notes in Computer Science. PRIMA 2020, Japan, Non-EU. Springer Nature Switzerland AG. https://doi.org/10.1007/978-3-030-69322-0
• NASCaps / Marchisio, A., Massa, A., Mrazek, V., Bussolino, B., Martina, M., & Shafique, M. (2020). NASCaps. In Proceedings of the 39th International Conference on Computer-Aided Design. 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Virtual Conference, Austria. IEEE. https://doi.org/10.1145/3400302.3415731
• ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations / Marchisio, A., Mrazek, V., Hanif, M. A., & Shafique, M. (2020). ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, EU. IEEE. https://doi.org/10.23919/date48585.2020.9116393
• Cross-layer approaches for improving the dependability of deep learning systems / Hanif, M. A., Hoang, L.-H., & Shafique, M. (2020). Cross-layer approaches for improving the dependability of deep learning systems. In Proceedings of the 23th International Workshop on Software and Compilers for Embedded Systems. 2020 23th International Workshop on Software and Compilers for Embedded Systems (SCOPES), St. Goar, Germany, EU. ACM. https://doi.org/10.1145/3378678.3391884
• Dependable Deep Learning: Towards Cost-Efficient Resilience of Deep Neural Network Accelerators against Soft Errors and Permanent Faults / Hanif, M. A., & Shafique, M. (2020). Dependable Deep Learning: Towards Cost-Efficient Resilience of Deep Neural Network Accelerators against Soft Errors and Permanent Faults. In 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), Napoli, Italy, EU. IEEE. https://doi.org/10.1109/iolts50870.2020.9159734
• Exploiting Vulnerabilities in Deep Neural Networks: Adversarial and Fault-Injection Attacks / Khalid, F., Hanif, M. A., & Shafique, M. (2020). Exploiting Vulnerabilities in Deep Neural Networks: Adversarial and Fault-Injection Attacks. In Proceedings of the Fifth International Conferenceon Cyber-Technologies and Cyber-Systems (pp. 24–29). http://hdl.handle.net/20.500.12708/55602
• Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities / Morid Ahmadi, M., Khalid, F., & Shafique, M. (2020). Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities. In Proceedings of the Fifth International Conferenceon Cyber-Technologies and Cyber-Systems (pp. 1–6). http://hdl.handle.net/20.500.12708/55599
• Proactive Aging Mitigation in CGRAs through Utilization-Aware Allocation / Brandalero, M., Lignati, B. N., Beck, A. C. S., Shafique, M., & Hübner, M. (2020). Proactive Aging Mitigation in CGRAs through Utilization-Aware Allocation. In Proceedings of 2020 57th ACM/IEEE Design Automation Conference (DAC) (pp. 1–6). IEEE. http://hdl.handle.net/20.500.12708/55584
• Is Spiking Secure? A Comparative Study on the Security Vulnerabilities of Spiking and Deep Neural Networks / Marchisio, A., Nanfa, G., Khalid, F., Hanif, M. A., Martina, M., & Shafique, M. (2020). Is Spiking Secure? A Comparative Study on the Security Vulnerabilities of Spiking and Deep Neural Networks. In Proceedings of 2020 International Joint Conference on Neural Networks (IJCNN) (pp. 1–8). IEEE. http://hdl.handle.net/20.500.12708/55583
• FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks / Marchisio, A., Bussolino, B., Colucci, A., Hanif, M. A., Martina, M., Masera, G., & Shafique, M. (2020). FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks. In Proceedings of 2020 International Joint Conference on Neural Networks (IJCNN) (pp. 1–8). IEEE. http://hdl.handle.net/20.500.12708/55582
• Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks / Marchisio, A., Bussolino, B., Colucci, A., Martina, M., Masera, G., & Shafique, M. (2020). Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks. In Proceedings of 2020 57th ACM/IEEE Design Automation Conference (DAC) (pp. 1–6). IEEE. http://hdl.handle.net/20.500.12708/55581
• PEMACx: A Probabilistic Error Analysis Methodology for Adders with Cascaded Approximate Units / Hanif, M. A., Hafiz, R., Hasan, O., & Shafique, M. (2020). PEMACx: A Probabilistic Error Analysis Methodology for Adders with Cascaded Approximate Units. In 2020 57th ACM/IEEE Design Automation Conference (DAC). 2020 57th ACM/IEEE Design Automation Conference (DAC), San Fransisco, USA (Virtual), Non-EU. IEEE. https://doi.org/10.1109/dac18072.2020.9218678
• Power-Aware Fault-Tolerance for Embedded Systems / Salehi, M., Kriebel, F., Rehman, S., & Shafique, M. (2020). Power-Aware Fault-Tolerance for Embedded Systems. In J. Henkel & N. Dutt (Eds.), Dependable Embedded Systems (pp. 565–588). Springer Nature Switzerland AG. https://doi.org/10.1007/978-3-030-52017-5_24
• Fault-Tolerant Computing with Heterogeneous Hardening Modes / Kriebel, F., Khalid, F., Prabakaran, B. S., Rehman, S., & Shafique, M. (2020). Fault-Tolerant Computing with Heterogeneous Hardening Modes. In J. Henkel & N. Dutt (Eds.), Dependable Embedded Systems (pp. 161–180). Springer Nature Switzerland AG. https://doi.org/10.1007/978-3-030-52017-5_7
• Dependable Software Generation and Execution on Embedded Systems / Kriebel, F., Chen, K.-H., Rehman, S., Henkel, J., Chen, J.-J., & Shafique, M. (2020). Dependable Software Generation and Execution on Embedded Systems. In J. Henkel & N. Dutt (Eds.), Dependable Embedded Systems (pp. 139–160). Springer Nature Switzerland AG. https://doi.org/10.1007/978-3-030-52017-5_6
• RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience / Herkersdorf, A., Engel, M., Glaß, M., Henkel, J., Kleeberger, V. B., Kühn, J. M., Marwedel, P., Mueller-Gritschneder, D., Nassif, S. R., Rehman, S., Rosenstiel, W., Schlichtmann, U., Shafique, M., Teich, J., Wehn, N., & Weis, C. (2020). RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience. In J. Henkel & N. Dutt (Eds.), Dependable Embedded Systems (pp. 1–27). Springer Nature Switzerland AG. https://doi.org/10.1007/978-3-030-52017-5_1

2019

• Verification of Randomized Consensus Algorithms Under Round-Rigid Adversaries / Bertrand, N., Konnov, I., Lazić, M., & Widder, J. (2019). Verification of Randomized Consensus Algorithms Under Round-Rigid Adversaries. In W. Fokkink & R. van Glabbeek (Eds.), 30th International Conference on Concurrency Theory (pp. 33:1-33:15). Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany. https://doi.org/10.4230/LIPIcs.CONCUR.2019.33
• Verifying Safety of Synchronous Fault-Tolerant Algorithms by Bounded Model Checking / Stoilkovska, I., Konnov, I., Widder, J., & Zuleger, F. (2019). Verifying Safety of Synchronous Fault-Tolerant Algorithms by Bounded Model Checking. In International Conference on Tools and Algorithms for the Construction and Analysis of Systems (pp. 357–374). Springer. http://hdl.handle.net/20.500.12708/56804
• An Experimental Study of Metastability-Induced Glitching Behavior / Polzer, T., Huemer, F., & Steininger, A. (2019). An Experimental Study of Metastability-Induced Glitching Behavior. Journal of Circuits, Systems, and Computers, 28(supp01), 1940006. https://doi.org/10.1142/s0218126619400061
• A Characterization of Consensus Solvability for Closed Message Adversaries / Winkler, K., Schmid, U., & Moses, Y. (2019). A Characterization of Consensus Solvability for Closed Message Adversaries. In P. Felber, R. Friedman, S. Gilbert, & A. Miller (Eds.), 23rd International Conference on Principles of Distributed Systems (pp. 17:1-17:16). Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/LIPIcs.OPODIS.2019.17
• Sustainable Security & Safety: Challenges and Opportunities / Paverd, A., Völp, M., Brasser, F., Schunter, M., Asokan, N., Sadeghi, A.-R., Esteves-Verissimo, P., Steininger, A., & Holz, T. (2019). Sustainable Security & Safety: Challenges and Opportunities. In M. Asplund & M. Paulitsch (Eds.), Proceedings 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems (CERTS 2019) (p. 13). Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/OASIcs.CERTS.2019.4
  Project: Intel CARS (2017–2019)
• SalvageDNN: Salvaging Deep Neural Network Accelerators with Permanent Faults through Saliency-driven Fault-aware Mapping / Abdullah Hanif, M., & Shafique, M. (2019). SalvageDNN: Salvaging Deep Neural Network Accelerators with Permanent Faults through Saliency-driven Fault-aware Mapping. Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences, 378(2164), 20190164. https://doi.org/10.1098/rsta.2019.0164
• ECAx: Balancing Error Correction Costs in Approximate Accelerators / Castro-Godínez, J., Shafique, M., & Henkel, J. (2019). ECAx: Balancing Error Correction Costs in Approximate Accelerators. ACM Transactions on Embedded Computing Systems, 18(5s), 1–20. https://doi.org/10.1145/3358179
• m-SAAC: Multi-stage Adaptive Approximation Control to Select Approximate Computing Modes for Vision Applications / Amjad, R., Hafiz, R., Ilyas, M. U., Younis, M. S., & Shafique, M. (2019). m-SAAC: Multi-stage Adaptive Approximation Control to Select Approximate Computing Modes for Vision Applications. Microelectronics Journal, 91, 84–91. https://doi.org/10.1016/j.mejo.2019.07.010
• Towards Model Checking-Driven Fair Comparison of Dynamic Thermal Management Techniques under Multi-Threaded Workloads / Bukhari, S. A. A., Khalid, F., Hasan, O., Shafique, M., & Henkel, J. (2019). Towards Model Checking-Driven Fair Comparison of Dynamic Thermal Management Techniques under Multi-Threaded Workloads. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(8), 1725–1738. https://doi.org/10.1109/tcad.2019.2921313
• X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture / Akbari, O., Kamal, M., Afzali-Kusha, A., Pedram, M., & Shafique, M. (2019). X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(10), 2558–2571. https://doi.org/10.1109/tcad.2019.2937738
• Application and Thermal-reliability-aware Reinforcement Learning Based Multi-core Power Management / Dinakarrao, S. M. P., Joseph, A., Haridass, A., Shafique, M., Henkel, J., & Homayoun, H. (2019). Application and Thermal-reliability-aware Reinforcement Learning Based Multi-core Power Management. ACM Journal on Emerging Technologies in Computing Systems, 15(4), 1–19. https://doi.org/10.1145/3323055
• MACISH: Designing Approximate MAC Accelerators With Internal-Self-Healing / Gillani, G. A., Hanif, M. A., Verstoep, B., Gerez, S. H., Shafique, M., & Kokkeler, A. B. J. (2019). MACISH: Designing Approximate MAC Accelerators With Internal-Self-Healing. IEEE Access, 7, 77142–77160. https://doi.org/10.1109/access.2019.2920335
• Self-Compensating Accelerators for Efficient Approximate Computing / Mazahir, S., Hasan, O., & Shafique, M. (2019). Self-Compensating Accelerators for Efficient Approximate Computing. Microelectronics Journal, 88, 9–17. https://doi.org/10.1016/j.mejo.2019.03.008
• On the Effect of Approximate-Computing in Motion Estimation / Paltrinieri, A., Peloso, R., Masera, G., Shafique, M., & Martina, M. (2019). On the Effect of Approximate-Computing in Motion Estimation. Journal of Low Power Electronics, 15(1), 40–50. https://doi.org/10.1166/jolpe.2019.1592
• Computer-aided arrhythmia diagnosis with bio-signal processing: A survey of trends and techniques / Dinakarrao, S. M. P., Jantsch, A., & Shafique, M. (2019). Computer-aided arrhythmia diagnosis with bio-signal processing: A survey of trends and techniques. ACM Computing Surveys, 52(2), 1–37. https://doi.org/10.1145/3297711
• Special Issue "Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018" / Krstic, M., Jones, I., Steininger, A., & Függer, M. (2019). Special Issue “Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018.” Journal of Low Power Electronics and Applications, 9(2), 2. http://hdl.handle.net/20.500.12708/143834
• Consensus in rooted dynamic networks with short-lived stability / Winkler, K., Schwarz, M., & Schmid, U. (2019). Consensus in rooted dynamic networks with short-lived stability. Distributed Computing, 32(5), 443–458. https://doi.org/10.1007/s00446-019-00348-0
• Novel Approaches for Efficient Delay-Insensitive Communication / Huemer, F., & Steininger, A. (2019). Novel Approaches for Efficient Delay-Insensitive Communication. Journal of Low Power Electronics and Applications, 9(2), 16. https://doi.org/10.3390/jlpea9020016
• On Linear-Time Data Dissemination in Dynamic Rooted Trees / Zeiner, M., Schwarz, M., & Schmid, U. (2019). On Linear-Time Data Dissemination in Dynamic Rooted Trees. Discrete Applied Mathematics, 255, 307–319. https://doi.org/10.1016/j.dam.2018.08.015
• A Roadmap Toward the Resilient Internet of Things for Cyber-Physical Systems / Ratasich, D., Khalid, F., Geissler, F., Grosu, R., Shafique, M., & Bartocci, E. (2019). A Roadmap Toward the Resilient Internet of Things for Cyber-Physical Systems. IEEE Access, 7, 13260–13283. https://doi.org/10.1109/access.2019.2891969
• Maehara-style Modal Nested Calculi / Kuznets, R., & Straßburger, L. (2019). Maehara-style Modal Nested Calculi. Archive for Mathematical Logic, 58(3–4), 359–385. https://doi.org/10.1007/s00153-018-0636-1
• An Overview of Recent Results for Consensus in Directed Dynamic Networks / Winkler, K., & Schmid, U. (2019). An Overview of Recent Results for Consensus in Directed Dynamic Networks. Bulletin of the EATCS, 128, 30. http://hdl.handle.net/20.500.12708/143248
• Design and Implementation of the Bachelor with Honors Program at TU Wien / Schmid, U. (2019). Design and Implementation of the Bachelor with Honors Program at TU Wien. Journal of the European Honors Council, 3(2). https://doi.org/10.31378/jehc.3.2
• Unified (A)Synchronous Circuit Development / Paulweber, P., Maier, J., & Cortadella, J. (2019). Unified (A)Synchronous Circuit Development. 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), Hirosaki, Japan, Non-EU. http://hdl.handle.net/20.500.12708/86909
• Translating Quantitative Semantic Bounds into Nested Sequents / Kuznets, R., & Lellmann, B. (2019). Translating Quantitative Semantic Bounds into Nested Sequents. Fifth TICAMORE MEETING, Wien, Austria. http://hdl.handle.net/20.500.12708/86976
• Time and Retrocausality in Distributed Systems / Kuznets, R. (2019). Time and Retrocausality in Distributed Systems. Goedel’s Legacy, Wien, Austria. http://hdl.handle.net/20.500.12708/86975
• Digital Modeling of Asynchronous Integrated Circuits / Schmid, U. (2019). Digital Modeling of Asynchronous Integrated Circuits. 2nd Workshop on Hardware Design and Theory (https://sites.google.com/view/motimedina/hdt-2019, colocated with DISC 2019), Budapest, EU. http://hdl.handle.net/20.500.12708/86974
• Byzantine Causal Cone / Kuznets, R., Prosperi, L., Schmid, U., & Fruzsa, K. (2019). Byzantine Causal Cone. Workshop on Formal Reasoning in Distributed Algorithms (FRiDA), Wien, Austria. http://hdl.handle.net/20.500.12708/86905
• Causality in the Age of Fake News / Kuznets, R. (2019). Causality in the Age of Fake News. Seminar “Logic and Theoretical Computer Science”, University of Bern (2019), Bern, Non-EU. http://hdl.handle.net/20.500.12708/86904
• Extrapolating Interpolation / Kuznets, R. (2019). Extrapolating Interpolation. Proof Theory in Logic workshop, Utrecht, EU. http://hdl.handle.net/20.500.12708/86880
• A Systematic Approach to Clock Failure Detection / Steininger, A., & Schwendinger, M. (2019). A Systematic Approach to Clock Failure Detection. In 2019 Austrochip Workshop on Microelectronics (Austrochip). Austrochip Workshop on Microelectronics, Wien, Austria. https://doi.org/10.1109/austrochip.2019.00018
  Project: Intel CARS (2017–2019)
• CapsAttacks: Robust and Imperceptible Adversarial Attacks on Capsule Networks / Marchisio, A., Nanfa, G., Khalid, F., Hanif, M. A., Martina, M., & Shafique, M. (2019). CapsAttacks: Robust and Imperceptible Adversarial Attacks on Capsule Networks. In Proceedings of Workshop on Uncertainty and Robustness in Deep Learning (UDL) 2019 at ICML’19 (pp. 1–9). http://hdl.handle.net/20.500.12708/58025
• FAdeML: Understanding the Impact of Pre-Processing Noise Filtering on Adversarial Machine Learning / Khalid, F., Hanif, M. A., Rehman, S., Qadir, J., & Shafique, M. (2019). FAdeML: Understanding the Impact of Pre-Processing Noise Filtering on Adversarial Machine Learning. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE’19), Florence, Italy, EU. IEEE. https://doi.org/10.23919/date.2019.8715141
• CapsAcc: An Efficient Hardware Accelerator for CapsuleNets with Data Reuse / Marchisio, A., Hanif, M. A., & Shafique, M. (2019). CapsAcc: An Efficient Hardware Accelerator for CapsuleNets with Data Reuse. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE’19), Florence, Italy, EU. IEEE. https://doi.org/10.23919/date.2019.8714922
• TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration / Brandalero, M., Shafique, M., Carro, L., & Beck, A. C. S. (2019). TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE’19), Florence, Italy, EU. IEEE. https://doi.org/10.23919/date.2019.8715121
• TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint / Abbassi, I. H., Khalid, F., Rehman, S., Kamboh, A. M., Jantsch, A., Garg, S., & Shafique, M. (2019). TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE’19), Florence, Italy, EU. IEEE. https://doi.org/10.23919/date.2019.8714829
• Thermal-Awareness in a Soft Error Tolerant Architecture / Hussain, S., Shafique, M., & Henkel, J. (2019). Thermal-Awareness in a Soft Error Tolerant Architecture. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE’19), Florence, Italy, EU. IEEE. https://doi.org/10.23919/date.2019.8715105
• A Fine-Grained Soft Error Resilient Architecture under Power Considerations / Hussain, S., Shafique, M., & Henkel, J. (2019). A Fine-Grained Soft Error Resilient Architecture under Power Considerations. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2019 IEEE/ACM Design, Automation and Test in Europe Conference (DATE’19), Florence, Italy, EU. IEEE. https://doi.org/10.23919/date.2019.8714797
• ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining / Mrazek, V., Vasicek, Z., Sekanina, L., Hanif, M. A., & Shafique, M. (2019). ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. In Proceeding of 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’19) (pp. 1–8). IEEE. http://hdl.handle.net/20.500.12708/58006
• MemGANs: Memory Management for Energy-Efficient Acceleration of Complex Computations in Hardware Architectures for Generative Adversarial Networks / Hanif, M. A., Zuhaib Akbar, M., Ahmed, R., Rehman, S., Jantsch, A., & Shafique, M. (2019). MemGANs: Memory Management for Energy-Efficient Acceleration of Complex Computations in Hardware Architectures for Generative Adversarial Networks. In 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED). 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Lausanne, Switzerland, EU. IEEE. https://doi.org/10.1109/islped.2019.8824833
• TrISec: Training Data-Unaware Imperceptible Security Attacks on Deep Neural Networks / Khalid, F., Hanif, M. A., Rehman, S., Ahmed, R., & Shafique, M. (2019). TrISec: Training Data-Unaware Imperceptible Security Attacks on Deep Neural Networks. In 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece, EU. IEEE. https://doi.org/10.1109/iolts.2019.8854425
• Topological Characterization of Consensus under General Message Adversaries / Nowak, T., Schmid, U., & Winkler, K. (2019). Topological Characterization of Consensus under General Message Adversaries. In Proceedings of the 2019 ACM Symposium on Principles of Distributed Computing. 38th ACM Symposium on Principles of Distributed Computing (PODC’19), Toronto, Canada, Non-EU. ACM. https://doi.org/10.1145/3293611.3331624
• QuSecNets: Quantization-based Defense Mechanism for Securing Deep Neural Network against Adversarial Attacks / Khalid, F., Ali, H., Tariq, H., Hanif, M. A., Rehman, S., Ahmed, R., & Shafique, M. (2019). QuSecNets: Quantization-based Defense Mechanism for Securing Deep Neural Network against Adversarial Attacks. In 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece, EU. IEEE. https://doi.org/10.1109/iolts.2019.8854377
• Towards Scalable Lifetime Reliability Management for Dark Silicon Manycore Systems / Rathore, V., Chaturvedi, V., Singh, A. K., Srikanthan, T., & Shafique, M. (2019). Towards Scalable Lifetime Reliability Management for Dark Silicon Manycore Systems. In 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece, EU. IEEE. https://doi.org/10.1109/iolts.2019.8854454
• Studying Aging and Soft Error Mitigation Jointly under Constrained Scenarios in Multi-Cores / Kriebel, F., Rehman, S., & Shafique, M. (2019). Studying Aging and Soft Error Mitigation Jointly under Constrained Scenarios in Multi-Cores. In 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS). 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece, EU. IEEE. https://doi.org/10.1109/iolts.2019.8854444
• Deep Learning for Edge Computing: Current Trends, Cross-Layer Optimizations, and Open Research Challenges / Marchisio, A., Hanif, M. A., Khalid, F., Plastiras, G., Kyrkou, C., Theocharides, T., & Shafique, M. (2019). Deep Learning for Edge Computing: Current Trends, Cross-Layer Optimizations, and Open Research Challenges. In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Miami, USA, Non-EU. IEEE. https://doi.org/10.1109/isvlsi.2019.00105
• Causality and Epistemic Reasoning in Byzantine Multi-Agent Systems / Kuznets, R., Prosperi, L., Schmid, U., & Fruzsa, K. (2019). Causality and Epistemic Reasoning in Byzantine Multi-Agent Systems. In L. Moss (Ed.), Electronic Proceedings in Theoretical Computer Science (pp. 293–312). Electronic Proceedings in Theoretical Computer Science. https://doi.org/10.4204/eptcs.297.19
• XBioSiP / Prabakaran, B. S., Rehman, S., & Shafique, M. (2019). XBioSiP. In Proceedings of the 56th Annual Design Automation Conference 2019. 2019 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, USA, Non-EU. IEEE. https://doi.org/10.1145/3316781.3317933
• CANN / Hanif, M. A., Khalid, F., & Shafique, M. (2019). CANN. In Proceedings of the 56th Annual Design Automation Conference 2019. 2019 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, USA, Non-EU. IEEE. https://doi.org/10.1145/3316781.3317787
• autoAx / Mrazek, V., Hanif, M. A., Vasicek, Z., Sekanina, L., & Shafique, M. (2019). autoAx. In Proceedings of the 56th Annual Design Automation Conference 2019. 2019 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, USA, Non-EU. IEEE. https://doi.org/10.1145/3316781.3317781
• Security Vulnerabilities of Deep, Capsule and Spiking Neural Networks against Adversarial Attacks / Marchisio, A., Nanfa, G., Martina, M., & Shafique, M. (2019). Security Vulnerabilities of Deep, Capsule and Spiking Neural Networks against Adversarial Attacks. In Proceedings of IEEE International Workshop on Robust and Trustworthy Machine Learning (RTML) 2019 (pp. 1–4). http://hdl.handle.net/20.500.12708/55718
• Building Robust Machine Learning Systems / Zang, J. (Jun), Liu, K., Khalid, F., Hanif, M. A., Rehman, S., Theocharides, T., Artussi, A., Shafique, M., & Garg, S. (2019). Building Robust Machine Learning Systems. In Proceedings of the 56th Annual Design Automation Conference 2019. 2019 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, USA, Non-EU. IEEE. https://doi.org/10.1145/3316781.3323472
• Life Guard: A Reinforcement Learning-Based Task Mapping Strategy for Performance-Centric Aging Managemen / Rathore, V., Chaturvedi, V., Singh, A. K., Srikanthan, T., & Shafique, M. (2019). Life Guard: A Reinforcement Learning-Based Task Mapping Strategy for Performance-Centric Aging Managemen. In Proceedings of the 56th Annual Design Automation Conference 2019. 2019 56th ACM/IEEE Design Automation Conference (DAC), Las Vegas, USA, Non-EU. IEEE. https://doi.org/10.1145/3316781.3317849
• A Topological View of Partitioning Arguments: Reducing k-Set Agreement to Consensus / Rincon Galeana, H., Winkler, K., Schmid, U., & Rajsbaum, S. (2019). A Topological View of Partitioning Arguments: Reducing k-Set Agreement to Consensus. In Lecture Notes in Computer Science (pp. 307–322). Lecture Notes in Computer Science / Springer. https://doi.org/10.1007/978-3-030-34992-9_25
• Hope for Epistemic Reasoning with Faulty Agents! / Fruzsa, K. (2019). Hope for Epistemic Reasoning with Faulty Agents! In ESSLLI 2019 Student Session (pp. 169–180). http://hdl.handle.net/20.500.12708/56972
• Epistemic Reasoning with Byzantine-Faulty Agents / Kuznets, R., Prosperi, L., Schmid, U., & Fruzsa, K. (2019). Epistemic Reasoning with Byzantine-Faulty Agents. In A. Herzig & A. Popescu (Eds.), Frontiers of Combining Systems (pp. 259–276). Springer. https://doi.org/10.1007/978-3-030-29007-8_15
• 2019 Principles of Distributed Computing Doctoral Dissertation Award / Jayanti, P., Lynch, N. A., Patt-Shamir, B., & Schmid, U. (2019). 2019 Principles of Distributed Computing Doctoral Dissertation Award. In Proceedings of the 2019 ACM Symposium on Principles of Distributed Computing. ACM. https://doi.org/10.1145/3293611.3341565
• Fault-tolerant High-Performance Clock Distribution / Kinali, A., Lenzen, C., & Perner, M. (2019). Fault-tolerant High-Performance Clock Distribution (TUW-278925). http://hdl.handle.net/20.500.12708/39734
• A Topological View of Partitioning Arguments: Reducing k-Set Agreement to Consensus / Rincon Galeana, H., Winkler, K., Schmid, U., & Rajsbaum, S. (2019). A Topological View of Partitioning Arguments: Reducing k-Set Agreement to Consensus (TUW-281149). http://hdl.handle.net/20.500.12708/39728
• Knowledge in Byzantine Message-Passing Systems I: Framework and the Causal Cone / Prosperi, L., Kuznets, R., Schmid, U., Fruzsa, K., & Gréaux, L. (2019). Knowledge in Byzantine Message-Passing Systems I: Framework and the Causal Cone (TUW-260549). http://hdl.handle.net/20.500.12708/39204
• Through an Inference Rule, Darkly / Kuznets, R. (2019). Through an Inference Rule, Darkly. In S. Centrone, S. Negri, D. Sarikaya, & P. Schuster (Eds.), Mathesis Universalis, Computability and Proof (pp. 131–158). Springer International Publishing. https://doi.org/10.1007/978-3-030-20447-1_10
• Hardware–Software Approximations for Deep Neural Networks / Hanif, M. A., Javed, M. U., Hafiz, R., Rehman, S., & Shafique, M. (2019). Hardware–Software Approximations for Deep Neural Networks. In Approximate Circuits (pp. 269–288). Springer International Publishing. https://doi.org/10.1007/978-3-319-99322-5_13
• Approximate Multi-Accelerator Tiled Architecture for Energy-Efficient Motion Estimation / Prabakaran, B. S., El-Harouni, W., Rehman, S., & Shafique, M. (2019). Approximate Multi-Accelerator Tiled Architecture for Energy-Efficient Motion Estimation. In Approximate Circuits (pp. 249–268). Springer International Publishing. https://doi.org/10.1007/978-3-319-99322-5_12
• Probabilistic Error Analysis of Approximate Adders and Multipliers / Mazahir, S., Ayub, M. K., Hasan, O., & Shafique, M. (2019). Probabilistic Error Analysis of Approximate Adders and Multipliers. In Approximate Circuits (pp. 99–120). Springer International Publishing. https://doi.org/10.1007/978-3-319-99322-5_5
• Heterogeneous Approximate Multipliers: Architectures and Design Methodologies / Rehman, S., Prabakaran, B. S., El-Harouni, W., Shafique, M., & Henkel, J. (2019). Heterogeneous Approximate Multipliers: Architectures and Design Methodologies. In Approximate Circuits (pp. 45–66). Springer International Publishing. https://doi.org/10.1007/978-3-319-99322-5_3
• Configurable Models and Design Space Exploration for Low-Latency Approximate Adders / Hanif, M. A., Hafiz, R., & Shafique, M. (2019). Configurable Models and Design Space Exploration for Low-Latency Approximate Adders. In Approximate Circuits (pp. 3–23). Springer International Publishing. https://doi.org/10.1007/978-3-319-99322-5_1
• Energy-Efficient Design of Advanced Machine Learning Hardware / Hanif, M. A., Hafiz, R., Javed, M. U., Rehman, S., & Shafique, M. (2019). Energy-Efficient Design of Advanced Machine Learning Hardware. In Machine Learning in VLSI Computer-Aided Design (pp. 647–678). Springer International Publishing. https://doi.org/10.1007/978-3-030-04666-8_21
• Approximate computing across the hardware and software stacks / Shafique, M., Hasan, O., Hafiz, R., Mazahir, S., Hanif, M. A., & Rehman, S. (2019). Approximate computing across the hardware and software stacks. In Many-Core Computing: Hardware and Software (pp. 497–522). IET. https://doi.org/10.1049/pbpc022e_ch20
• Logics of Proofs and Justifications / Kuznets, R., & Studer, T. (2019). Logics of Proofs and Justifications. College Publications. http://hdl.handle.net/20.500.12708/24606
• Approximate Circuits / Reda, S., & Shafique, M. (Eds.). (2019). Approximate Circuits. Springer International Publishing. https://doi.org/10.1007/978-3-319-99322-5

2018

• SmartDPM: Machine Learning-based Dynamic Power Management for Multi-Core Microprocessors / Pudukotai Dinakarrao, S. M., Jantsch, A., & Shafique, M. (2018). SmartDPM: Machine Learning-based Dynamic Power Management for Multi-Core Microprocessors. Journal of Low Power Electronics and Applications, 14(4), 460–474. https://doi.org/10.1166/jolpe.2018.1576
• Reachability in Parameterized Systems: All Flavors of Threshold Automata / Kukovec, J., Konnov, I., & Widder, J. (2018). Reachability in Parameterized Systems: All Flavors of Threshold Automata. In S. Schewe & L. Zhang (Eds.), 29th International Conference on Concurrency Theory (CONCUR 2018) (pp. 19:1-19:17). Schloss Dagstuhl - Leibniz-Zentrum für Informatik GmbH, Dagstuhl Publishing. https://doi.org/10.4230/LIPIcs.CONCUR.2018.19
• Gracefully degrading consensus and k-set agreement in directed dynamic networks / Biely, M., Robinson, P., Schmid, U., Schwarz, M., & Winkler, K. (2018). Gracefully degrading consensus and k-set agreement in directed dynamic networks. Theoretical Computer Science, 726, 41–77. https://doi.org/10.1016/j.tcs.2018.02.019
• TransportBuddy: Navigation in Human Accessible Spaces / Bader, M., Todoran, G., Beck, F., Binder, B., & Buchegger, K. (2018). TransportBuddy: Navigation in Human Accessible Spaces. In C. Landschützer, M. Fritz, & A. Wolfschluckner (Eds.), Proceedings of 7th Transport Research Arena TRA 2018 (p. 10). Zenodo. https://doi.org/10.5281/zenodo.1486646
• Statistical Model Checking of Relief Supply Location and Distribution in Natural Disaster Management / Iqbal, S., Sardar, M. U., Khalid, F., & Hasan, O. (2018). Statistical Model Checking of Relief Supply Location and Distribution in Natural Disaster Management. International Journal of Disaster Risk Reduction, 31, 1043–1053. https://doi.org/10.1016/j.ijdrr.2018.04.010
• Guest Editorial: Special Issue on Low-Power Dependable Computing / Zhu, D., Shafique, M., Lin, M., & Pasricha, S. (2018). Guest Editorial: Special Issue on Low-Power Dependable Computing. IEEE Transactions on Sustainable Computing, 3(3), 137–138. https://doi.org/10.1109/tsusc.2018.2813078
• Runtime Hardware Trojan Monitors Through Modeling Burst Mode Communication Using Formal Verification / Khalid, F., Hasan, S. R., Hasan, O., & Awwad, F. (2018). Runtime Hardware Trojan Monitors Through Modeling Burst Mode Communication Using Formal Verification. Integration, 61, 62–76. https://doi.org/10.1016/j.vlsi.2017.11.003
• Automated Competitive Analysis of Real-time Scheduling with Graph Games / Chatterjee, K., Pavlogiannis, A., Kößler, A., & Schmid, U. (2018). Automated Competitive Analysis of Real-time Scheduling with Graph Games. Real-Time Systems, 54(1), 166–207. https://doi.org/10.1007/s11241-017-9293-4
• Metastability-Containing Circuits / Friedrichs, S., Függer, M., & Lenzen, C. (2018). Metastability-Containing Circuits. IEEE Transactions on Computers, 67(8), 1167–1183. https://doi.org/10.1109/tc.2018.2808185
• X-DNNs: Systematic Cross-Layer Approximations for Energy-Efficient Deep Neural Networks / Hanif, M. A., Marchisio, A., Arif, T., Hafiz, R., Rehman, S., & Shafique, M. (2018). X-DNNs: Systematic Cross-Layer Approximations for Energy-Efficient Deep Neural Networks. Journal of Low Power Electronics, 14(4), 520–534. https://doi.org/10.1166/jolpe.2018.1575
• Run-Time Adaptive Power-Aware Reliability Management for Manycores / Salehi, M., Ejlali, A., & Shafique, M. (2018). Run-Time Adaptive Power-Aware Reliability Management for Manycores. IEEE Design and Test, 35(5), 36–44. https://doi.org/10.1109/mdat.2017.2775738
• Towards Approximate Computing for Coarse-Grained Reconfigurable Architectures / Akbari, O., Kamal, M., Afzali-Kusha, A., Pedram, M., & Shafique, M. (2018). Towards Approximate Computing for Coarse-Grained Reconfigurable Architectures. IEEE Micro, 38(6), 63–72. https://doi.org/10.1109/mm.2018.2873951
• Hybrid Scratchpad Video Memory Architecture for Energy-Efficient Parallel HEVC / Sampaio, F. M., Zatt, B., Shafique, M., Henkel, J., & Bampi, S. (2018). Hybrid Scratchpad Video Memory Architecture for Energy-Efficient Parallel HEVC. IEEE Transactions on Circuits and Systems for Video Technology, 29(10), 3046–3060. https://doi.org/10.1109/tcsvt.2018.2870825
• SquASH: Approximate Square-Accumulate with Self-Healing / Gillani, G. A., Hanif, M. A., Krone, M., Gerez, S. H., Shafique, M., & Kokkeler, A. B. J. (2018). SquASH: Approximate Square-Accumulate with Self-Healing. IEEE Access, 6, 49112–49128. https://doi.org/10.1109/access.2018.2868036
• adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning / Kanduri, A., Haghbayan, M.-H., Rahmani, A. M., Shafique, M., Jantsch, A., & Liljeberg, P. (2018). adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning. IEEE Transactions on Computers, 67(8), 1062–1077. https://doi.org/10.1109/tc.2018.2805683
• Adaptive Approximate Computing in Arithmetic Datapaths / Mazahir, S., Hasan, O., & Shafique, M. (2018). Adaptive Approximate Computing in Arithmetic Datapaths. IEEE Design and Test, 35(4), 65–74. https://doi.org/10.1109/mdat.2017.2772874
• Aging-Aware Workload Management on Embedded GPU Under Process Variation / Lee, H., Shafique, M., & Al Faruque, M. A. (2018). Aging-Aware Workload Management on Embedded GPU Under Process Variation. IEEE Transactions on Computers, 67(7), 920–933. https://doi.org/10.1109/tc.2018.2789904
• McSeVIC: A Model Checking Based Framework for Security Vulnerability Analysis of Integrated Circuits / Abbassi, I. H., Khalid, F., Hasan, O., Kamboh, A. M., & Shafique, M. (2018). McSeVIC: A Model Checking Based Framework for Security Vulnerability Analysis of Integrated Circuits. IEEE Access, 6, 32240–32257. https://doi.org/10.1109/access.2018.2846583
• Refined Metastability Characterization Using a Time-to-Digital Converter / Polzer, T., Huemer, F., & Steininger, A. (2018). Refined Metastability Characterization Using a Time-to-Digital Converter. Microelectronics Reliability, 80, 91–99. https://doi.org/10.1016/j.microrel.2017.11.017
• Interpolation using sequents and their generalisations / Kuznets, R. (2018). Interpolation using sequents and their generalisations. PhDs in Logic X, Prague, EU. http://hdl.handle.net/20.500.12708/86799
• What do Byzantine agents know? / Gréaux, L., Kuznets, R., Prosperi, L., & Schmid, U. (2018). What do Byzantine agents know? First joint workshop by the Mathematics and the Philosophy Research Institutes of UNAM, Mexiko-Stadt, Mexiko, Non-EU. http://hdl.handle.net/20.500.12708/86037
• 32nd International Symposium on Distributed Computing / Schmid, U., & Widder, J. (Eds.). (2018). 32nd International Symposium on Distributed Computing. Dagstuhl Publishing LIPICS. https://doi.org/10.4230/LIPIcs.DISC.2018.0
• ApproxCT: Approximate Clustering Techniques for Energy Efficient Computer Vision in Cyber-Physical Systems / Javed, R. H., Siddique, A., Hafiz, R., Hasan, O., & Shafique, M. (2018). ApproxCT: Approximate Clustering Techniques for Energy Efficient Computer Vision in Cyber-Physical Systems. In 2018 12th International Conference on Open Source Systems and Technologies (ICOSST). 2018 12th International Conference on Open Source Systems and Technologies (ICOSST), Lahore, Pakistan, Non-EU. IEEE. https://doi.org/10.1109/icosst.2018.8632191
• Hardware Trojan Based Security Issues in Home Area Network: a Testbed Setup / Mohammed, H., Howell, J., Hasan, S. R., Guo, N., Khalid, F., & Elkeelany, O. (2018). Hardware Trojan Based Security Issues in Home Area Network: a Testbed Setup. In International Midwest Symposium on Circuits and Systems (pp. 1–4). IEEE. http://hdl.handle.net/20.500.12708/57754
• Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA / Huemer, F., Polzer, T., & Steininger, A. (2018). Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. In 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/ddecs.2018.00032
• Security for Machine Learning-based Systems: Attacks and Challenges during Training and Inference / Khalid, F., Hanif, M. A., Rehman, S., & Shafique, M. (2018). Security for Machine Learning-based Systems: Attacks and Challenges during Training and Inference. In 16th International Conference on Frontiers of Information Technology (FIT) (pp. 1–6). http://hdl.handle.net/20.500.12708/55714
• State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration / Schütz, M., Steininger, A., Huemer, F., & Lechner, J. (2018). State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/dft.2018.8602984
  Project: Intel CARS (2017–2019)
• Advanced Delay-Insensitive 4-Phase Protocols / Huemer, F., & Steininger, A. (2018). Advanced Delay-Insensitive 4-Phase Protocols. In 2018 Austrochip Workshop on Microelectronics (Austrochip). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/austrochip.2018.8520702
• Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication / Huemer, F., & Steininger, A. (2018). Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. In 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/async.2018.00014
• Tight Bounds for Asymptotic and Approximate Consensus / Függer, M., Nowak, T., & Schwarz, M. (2018). Tight Bounds for Asymptotic and Approximate Consensus. In Proceedings of the 2018 ACM Symposium on Principles of Distributed Computing. 37th ACM Symposium on Principles of Distributed Computing (PODC’18), Royal Holloway, University of London, Egham, United Kingdom, EU. ACM. https://doi.org/10.1145/3212734.3212762
• Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance / Fuegger, M., Kinali, A., Lenzen, C., & Wiederhake, B. (2018). Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance. In 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 24th IEEE International Symposium on Asynchronous Circuits and Systems, Wien, Austria. Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems. https://doi.org/10.1109/async.2018.00025
• Scalable Dynamic Task Scheduling on Adaptive Many-Core / Venkataramani, V., Pathania, A., Shafique, M., Mitra, T., & Henkel, J. (2018). Scalable Dynamic Task Scheduling on Adaptive Many-Core. In 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Hanoi, Vietnam, Non-EU. https://doi.org/10.1109/mcsoc2018.2018.00037
• An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding / Selvo, P., Masera, M., Peloso, R., Masera, G., Shafique, M., & Martina, M. (2018). An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding. In The 6th Conference on Applications in Electronics Pervading Industry, Environment and Society (ApplePies) (pp. 1–6). http://hdl.handle.net/20.500.12708/57604
• Intelligent Security Measures for Smart Cyber Physical Systems / Shafique, M., Khalid, F., & Rehman, S. (2018). Intelligent Security Measures for Smart Cyber Physical Systems. In 2018 21st Euromicro Conference on Digital System Design (DSD). 2018 21st Euromicro Conference on Digital System Design (DSD), Prague, Czech Republic, EU. https://doi.org/10.1109/dsd.2018.00058
• PruNet: Class-Blind Pruning Method For Deep Neural Networks / Marchisio, A., Hanif, M. A., Martina, M., & Shafique, M. (2018). PruNet: Class-Blind Pruning Method For Deep Neural Networks. In 2018 International Joint Conference on Neural Networks (IJCNN). IEEE International Joint Conference on Neural Networks (IJCNN), Montréal, Québec, Canada, Austria. https://doi.org/10.1109/ijcnn.2018.8489764
• Robust Machine Learning Systems: Reliability and Security for Deep Neural Networks / Hanif, M. A., Khalid, F., Putra, R. V. W., Rehman, S., & Shafique, M. (2018). Robust Machine Learning Systems: Reliability and Security for Deep Neural Networks. In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 24th IEEE International Symposium on On-Line Testing And Robust System Design (IOLTS’18), Platja D’Aro, Spain, EU. https://doi.org/10.1109/iolts.2018.8474192
• Robustness for Smart Cyber Physical Systems and Internet-of-Things: From Adaptive Robustness Methods to Reliability and Security for Machine Learning / Kriebel, F., Rehman, S., Hanif, M. A., Khalid, F., & Shafique, M. (2018). Robustness for Smart Cyber Physical Systems and Internet-of-Things: From Adaptive Robustness Methods to Reliability and Security for Machine Learning. In 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China, Non-EU. https://doi.org/10.1109/isvlsi.2018.00111
• Approximate On-The-Fly Coarse-Grained Reconfigurable Acceleration for General-Purpose Applications / Brandalero, M., S. Beck, A. C., Carro, L., & Shafique, M. (2018). Approximate On-The-Fly Coarse-Grained Reconfigurable Acceleration for General-Purpose Applications. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC). 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Fransisco, USA, Non-EU. https://doi.org/10.1109/dac.2018.8465930
• Area-Optimized Low-Latency Approximate Multipliers for FPGA-based Hardware Accelerators / Ullah, S., Rehman, S., Prabakaran, B. S., Kriebel, F., Hanif, M. A., Shafique, M., & Kumar, A. (2018). Area-Optimized Low-Latency Approximate Multipliers for FPGA-based Hardware Accelerators. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC). 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Fransisco, USA, Non-EU. https://doi.org/10.1109/dac.2018.8465781
• QoS-Aware Stochastic Power Management for Many-Cores / Pathania, A., Khdr, H., Shafique, M., Mitra, T., & Henkel, J. (2018). QoS-Aware Stochastic Power Management for Many-Cores. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC). 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Fransisco, USA, Non-EU. https://doi.org/10.1109/dac.2018.8465916
• Low Power Digital Clock Multipliers for Battery-Operated Internet of Things (IoT) Devices / Khalid, F., Nanjiani, S., Hasan, S. R., Hasan, O., Awwad, F., & Shafique, M. (2018). Low Power Digital Clock Multipliers for Battery-Operated Internet of Things (IoT) Devices. In 2018 IEEE International Symposium on Circuits and Systems (ISCAS). 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, EU. https://doi.org/10.1109/iscas.2018.8351102
• Hardware and Software Techniques for Heterogeneous Fault-Tolerance / Rehman, S., Kriebel, F., Prabakaran, B. S., Khalid, F., & Shafique, M. (2018). Hardware and Software Techniques for Heterogeneous Fault-Tolerance. In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design (IOLTS), Platja d’Aro, Spain, EU. https://doi.org/10.1109/iolts.2018.8474219
• HiMap: A hierarchical mapping approach for enhancing lifetime reliability of dark silicon manycore systems / Rathore, V., Chaturvedi, V., Singh, A. K., Srikanthan, T., R., R., Lam, S.-K., & Shafique, M. (2018). HiMap: A hierarchical mapping approach for enhancing lifetime reliability of dark silicon manycore systems. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE’18), Dresden, Deutschland, EU. https://doi.org/10.23919/date.2018.8342153
• AdAM: Adaptive approximation management for the non-volatile memory hierarchies / Teimoori, M. T., Hanif, M. A., Ejlali, A., & Shafique, M. (2018). AdAM: Adaptive approximation management for the non-volatile memory hierarchies. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE’18), Dresden, Deutschland, EU. https://doi.org/10.23919/date.2018.8342113
• PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture / Akbari, O., Kamal, M., Afzali-Kusha, A., Pedram, M., & Shafique, M. (2018). PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE’18), Dresden, Deutschland, EU. https://doi.org/10.23919/date.2018.8342045
• Compiler-driven error analysis for designing approximate accelerators / Castro-Godinez, J., Esser, S., Shafique, M., Pagani, S., & Henkel, J. (2018). Compiler-driven error analysis for designing approximate accelerators. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE’18), Dresden, Deutschland, EU. https://doi.org/10.23919/date.2018.8342163
• Error resilience analysis for systematically employing approximate computing in convolutional neural networks / Hanif, M. A., Hafiz, R., & Shafique, M. (2018). Error resilience analysis for systematically employing approximate computing in convolutional neural networks. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE’18), Dresden, Deutschland, EU. https://doi.org/10.23919/date.2018.8342139
• DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems / Prabakaran, B. S., Rehman, S., Hanif, M. A., Ullah, S., Mazaheri, G., Kumar, A., & Shafique, M. (2018). DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE’18), Dresden, Deutschland, EU. https://doi.org/10.23919/date.2018.8342140
• An overview of next-generation architectures for machine learning: Roadmap, opportunities and challenges in the IoT era / Shafique, M., Theocharides, T., Bouganis, C.-S., Hanif, M. A., Khalid, F., Hafiz, R., & Rehman, S. (2018). An overview of next-generation architectures for machine learning: Roadmap, opportunities and challenges in the IoT era. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE’18), Dresden, Deutschland, EU. https://doi.org/10.23919/date.2018.8342120
• HW/SW co-design and co-optimizations for deep learning / Marchisio, A., Putra, R. V. W., Hanif, M. A., & Shafique, M. (2018). HW/SW co-design and co-optimizations for deep learning. In Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications. Workshop on INTelligent Embedded Systems Architectures and Applications (INTESA), at the Embedded Systems Week (ESWeek), Turin, Italy, EU. https://doi.org/10.1145/3285017.3285022
• Verifying nonlinear analog and mixed-signal circuits with inputs / Fan, C., Meng, Y., Maier, J., Bartocci, E., Mitra, S., & Schmid, U. (2018). Verifying nonlinear analog and mixed-signal circuits with inputs. In IFAC-PapersOnLine (pp. 241–246). IFAC-PapersOnLine. https://doi.org/10.1016/j.ifacol.2018.08.041
• On linear-time data dissemination in dynamic trees / Zeiner, M., Schwarz, M., & Schmid, U. (2018). On linear-time data dissemination in dynamic trees. In CSASC 2018 - Book of Abstracts (p. 113). http://hdl.handle.net/20.500.12708/57537
• FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements / Hailesellasie, M., Hasan, S. R., Khalid, F., Wad, F. A., & Shafique, M. (2018). FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements. In 2018 IEEE International Symposium on Circuits and Systems (ISCAS). 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, EU. https://doi.org/10.1109/iscas.2018.8351283
• On Knowledge and Communication Complexity in Distributed Systems / Pfleger, D., & Schmid, U. (2018). On Knowledge and Communication Complexity in Distributed Systems. In Structural Information and Communication Complexity (pp. 312–330). Springer International Publishing. https://doi.org/10.1007/978-3-030-01325-7_27
• On the Strongest Message Adversary for Consensus in Directed Dynamic Networks / Schmid, U., Schwarz, M., & Winkler, K. (2018). On the Strongest Message Adversary for Consensus in Directed Dynamic Networks. In Structural Information and Communication Complexity (pp. 102–120). Springer International Publishing. https://doi.org/10.1007/978-3-030-01325-7_13
• Interpolation for Intermediate Logics via Hyper- and Linear Nested Sequents / Kuznets, R., & Lellmann, B. (2018). Interpolation for Intermediate Logics via Hyper- and Linear Nested Sequents. In G. Bezhanishvili, G. D´Agostino, G. Metcalfe, & T. Studer (Eds.), Advances in Modal Logic, Volume 12 (pp. 473–492). College Publications. http://hdl.handle.net/20.500.12708/57374
• Self-Stabilizing High-Speed Communication in Multi-Synchronous GALS Architectures / Perner, M., & Schmid, U. (2018). Self-Stabilizing High-Speed Communication in Multi-Synchronous GALS Architectures. In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). 24th IEEE International Symposium on On-Line Testing And Robust System Design (IOLTS’18), Platja D’Aro, Spain, EU. https://doi.org/10.1109/iolts.2018.8474221
• 2018 Edsger W. Dijkstra Prize in Distributed Computing / Afek, Y., Keidar, I., Patt-Shamir, B., Rajsbaum, S., Schmid, U., & Taubenfeld, G. (2018). 2018 Edsger W. Dijkstra Prize in Distributed Computing. In Proceedings of the 2018 ACM Symposium on Principles of Distributed Computing. ACM Press. https://doi.org/10.1145/3212734.3232540
• Communication-Closed Layers as Paradigm for Distributed Systems: A Manifesto / Dragoi, C., Lazić, M., & Widder, J. (2018). Communication-Closed Layers as Paradigm for Distributed Systems: A Manifesto. In Proceedings of the International Scientific Conference - Sinteza 2018. Sinteza 2018 International Scientific Conference on Information Technology and Data Related Research, Belgrad, Serbien, Non-EU. Singidunum University. https://doi.org/10.15308/sinteza-2018-131-138
• On Knowledge and Communication Complexity in Distributed Systems / Pfleger, D., & Schmid, U. (2018). On Knowledge and Communication Complexity in Distributed Systems (TUW-269752). http://hdl.handle.net/20.500.12708/39457
• On the Strongest Message Adversary for Consensus in Directed Dynamic Networks / Schwarz, M., & Schmid, U. (2018). On the Strongest Message Adversary for Consensus in Directed Dynamic Networks (TUW-269285). http://hdl.handle.net/20.500.12708/39450
• Self-Stabilizing High-Speed Communication in Multi-Synchronous GALS Architectures / Perner, M., & Schmid, U. (2018). Self-Stabilizing High-Speed Communication in Multi-Synchronous GALS Architectures (TUW-268547). http://hdl.handle.net/20.500.12708/39426
• Involution Tool / Öhlinger, D. (2018). Involution Tool (TUW-278633). http://hdl.handle.net/20.500.12708/39720
• FWF-Proposal DMAC: Digital Modeling of Asynchronous Integrated Circuits / Schmid, U. (2018). FWF-Proposal DMAC: Digital Modeling of Asynchronous Integrated Circuits (TUW-278607). http://hdl.handle.net/20.500.12708/39717
• Dark Silicon Aware Resource Management for Many-Core Systems / Khdr, H., Pagani, S., Shafique, M., & Henkel, J. (2018). Dark Silicon Aware Resource Management for Many-Core Systems. In Advances in Computers (pp. 127–170). Elsevier. https://doi.org/10.1016/bs.adcom.2018.03.002
• Advanced Techniques for Power, Energy, and Thermal Management for Clustered Manycores / Pagani, S., Chen, J.-J., Shafique, M., & Henkel, J. (2018). Advanced Techniques for Power, Energy, and Thermal Management for Clustered Manycores. Springer International Publishing. https://doi.org/10.1007/978-3-319-77479-4

2017

• Foreword / Steininger, A., Pawlak, A., & Stopjakova, V. (2017). Foreword. Journal of Circuits, Systems, and Computers, 26(08), Article 1702001. https://doi.org/10.1142/s0218126617020017
• Optimal Greedy Algorithm for Many-Core Scheduling / Pathania, A., Venkataramani, V., Shafique, M., Mitra, T., & Henkel, J. (2017). Optimal Greedy Algorithm for Many-Core Scheduling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(6), 1054–1058. https://doi.org/10.1109/tcad.2016.2618880
• Modeling the CMOS Inverter using Hybrid Systems / Maier, J. (2017). Modeling the CMOS Inverter using Hybrid Systems. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:3-10163
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• Setup for an Experimental Study of Radiation Effects in 65nm CMOS / Fritz, B., Veeravalli, V. S., Steininger, A., & Simek, V. (2017). Setup for an Experimental Study of Radiation Effects in 65nm CMOS. In 2017 Euromicro Conference on Digital System Design (DSD). 20th Euromicro Conference on Digital System Design, Wien, Austria. https://doi.org/10.1109/dsd.2017.60
• Synthesis of Distributed Algorithms with Parameterized Threshold Guards / Lazić, M., Konnov, I., Widder, J., & Bloem, R. (2017). Synthesis of Distributed Algorithms with Parameterized Threshold Guards. In J. Aspnes, A. Bessani, P. Felber, & J. Leitao (Eds.), 21st International Conference on Principles of Distributed Systems (OPODIS 2017) (pp. 32:1-32:20). LIPIcs-Leibniz International Proceedings in Informatics. https://doi.org/10.4230/LIPIcs.OPODIS.2017.32
• A Model for the Metastability Delay of Sequential Elements / Polzer, T., & Steininger, A. (2017). A Model for the Metastability Delay of Sequential Elements. Journal of Circuits, Systems, and Computers, 26(08), 1740010. https://doi.org/10.1142/s0218126617400102
• New transience bounds for max-plus linear systems / Charron-Bost, B., Függer, M., & Nowak, T. (2017). New transience bounds for max-plus linear systems. Discrete Applied Mathematics, 219, 83–99. https://doi.org/10.1016/j.dam.2016.11.003
• Probabilistic Error Analysis of Approximate Recursive Multipliers / Mazahir, S., Hasan, O., Hafiz, R., & Shafique, M. (2017). Probabilistic Error Analysis of Approximate Recursive Multipliers. IEEE Transactions on Computers, 66(11), 1982–1990. https://doi.org/10.1109/tc.2017.2709542
• Computing in the Dark Silicon Era: Current Trends and Research Challenges / Shafique, M., & Garg, S. (2017). Computing in the Dark Silicon Era: Current Trends and Research Challenges. IEEE Design and Test, 34(2), 8–23. https://doi.org/10.1109/mdat.2016.2633408
• Energy Efficiency for Clustered Heterogeneous Multicores / Pagani, S., Pathania, A., Shafique, M., Chen, J.-J., & Henkel, J. (2017). Energy Efficiency for Clustered Heterogeneous Multicores. IEEE Transactions on Parallel and Distributed Systems, 28(5), 1315–1330. https://doi.org/10.1109/tpds.2016.2623616
• Defragmentation of Tasks in Many-Core Architecture / Pathania, A., Venkataramani, V., Shafique, M., Mitra, T., & Henkel, J. (2017). Defragmentation of Tasks in Many-Core Architecture. ACM Transactions on Architecture and Code Optimization, 14(1), 1–21. https://doi.org/10.1145/3050437
• Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors / Li, T., Shafique, M., Ambrose, J. A., Henkel, J., & Parameswaran, S. (2017). Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. IEEE Transactions on Computers, 66(4), 647–660. https://doi.org/10.1109/tc.2016.2606378
• Application-Guided Power-Efficient Fault Tolerance for H.264 Context Adaptive Variable Length Coding / Shafique, M., Rehman, S., Kriebel, F., Khan, M. U. K., Zatt, B., Subramaniyan, A., Vizzotto, B. B., & Henkel, J. (2017). Application-Guided Power-Efficient Fault Tolerance for H.264 Context Adaptive Variable Length Coding. IEEE Transactions on Computers, 66(4), 560–574. https://doi.org/10.1109/tc.2016.2616313
• Probabilistic Error Modeling for Approximate Adders / Mazahir, S., Hasan, O., Hafiz, R., Shafique, M., & Henkel, J. (2017). Probabilistic Error Modeling for Approximate Adders. IEEE Transactions on Computers, 66(3), 515–530. https://doi.org/10.1109/tc.2016.2605382
• Power Density-Aware Resource Management for Heterogeneous Tiled Multicores / Khdr, H., Pagani, S., Sousa, E., Lari, V., Pathania, A., Hannig, F., Shafique, M., Teich, J., & Henkel, J. (2017). Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Transactions on Computers, 66(3), 488–501. https://doi.org/10.1109/tc.2016.2595560
• Thermal Safe Power (TSP): Efficient Power Budgeting for Heterogeneous Manycore Systems in Dark Silicon / Pagani, S., Khdr, H., Chen, J.-J., Shafique, M., Li, M., & Henkel, J. (2017). Thermal Safe Power (TSP): Efficient Power Budgeting for Heterogeneous Manycore Systems in Dark Silicon. IEEE Transactions on Computers, 66(1), 147–162. https://doi.org/10.1109/tc.2016.2564969
• A versatile architecture for long-term monitoring of single-event transient durations / Savulimedu Veeravalli, V., Steininger, A., & Schmid, U. (2017). A versatile architecture for long-term monitoring of single-event transient durations. Microprocessors and Microsystems, 53, 130–144. https://doi.org/10.1016/j.micpro.2017.07.007
• Para^2: Parameterized Path Reduction, Acceleration, and SMT for Reachability in Threshold-Guarded Distributed Algorithms / Konnov, I., Lazić, M., Veith, H., & Widder, J. (2017). Para^2: Parameterized Path Reduction, Acceleration, and SMT for Reachability in Threshold-Guarded Distributed Algorithms. Formal Methods in System Design, 51(2), 270–307. https://doi.org/10.1007/s10703-017-0297-4
• Guest Editors' Introduction: Computing in the Dark Silicon Era / Shafique, M., Garg, S., & Chandra, V. (2017). Guest Editors’ Introduction: Computing in the Dark Silicon Era. IEEE Design and Test, 34(2), 5–7. https://doi.org/10.1109/mdat.2017.2651065
• On the completeness of bounded model checking for threshold-based distributed algorithms: Reachability / Konnov, I., Veith, H., & Widder, J. (2017). On the completeness of bounded model checking for threshold-based distributed algorithms: Reachability. Information and Computation, 252, 95–109. https://doi.org/10.1016/j.ic.2016.03.006
• Approximate Networking for Universal Internet Access / Qadir, J., Sathiaseelan, A., Farooq, U., Usama, M., Imran, M., & Shafique, M. (2017). Approximate Networking for Universal Internet Access. Future Internet, 9(4), 94. https://doi.org/10.3390/fi9040094
• Approximate Computing across the Hardware and Software Stacks / Shafique, M. (2017). Approximate Computing across the Hardware and Software Stacks. Invited Talks at TU Eindhoven, TU Eindhoven, Netherlands, EU. http://hdl.handle.net/20.500.12708/86684
• Cross-Layer Approximate Computing: From Circuits to Applications / Shafique, M. (2017). Cross-Layer Approximate Computing: From Circuits to Applications. Invited Talks at University of Twente, University of Twente, Netherlands, EU. http://hdl.handle.net/20.500.12708/86683
• Low-Power Computing and Emerging Trends / Shafique, M. (2017). Low-Power Computing and Emerging Trends. CPS Summer School 2017, Porto Contr Ricerche, Alghero, Italy, EU. http://hdl.handle.net/20.500.12708/86679
• Enabling Extreme Energy-Efficiency through Brain-Inspired Computing Trends: From Approximate to Neural Processing / Shafique, M. (2017). Enabling Extreme Energy-Efficiency through Brain-Inspired Computing Trends: From Approximate to Neural Processing. 15th International Conference On Frontiers of Information Technology (FIT’17), Islamabad, Pakistan, Non-EU. http://hdl.handle.net/20.500.12708/86678
• Emerging Brain-Inspired Computing Trends: From Approximate Computing to Neural Processing / Shafique, M. (2017). Emerging Brain-Inspired Computing Trends: From Approximate Computing to Neural Processing. International Conference On Latest Trends in Electrical Engineering and Computing Technologies (INTELLECT’17), Karachi, Pakistan, Non-EU. http://hdl.handle.net/20.500.12708/86677
• Robust Heterogeneous Computing for CPS / Shafique, M. (2017). Robust Heterogeneous Computing for CPS. CPS Summer School 2017, Porto Contr Ricerche, Alghero, Italy, EU. http://hdl.handle.net/20.500.12708/86575
• The Byzantine Mind / Kuznets, R. (2017). The Byzantine Mind. Seminar Logic and Theoretical Computer Science, University of Bern (2017), Bern, Schweiz, Non-EU. http://hdl.handle.net/20.500.12708/86565
• Maehara-style Modal Nested Calculi / Kuznets, R., & Straßburger, L. (2017). Maehara-style Modal Nested Calculi (RR-9123). http://hdl.handle.net/20.500.12708/39305
• A Self-Healing Framework for Building Resilient Cyber-Physical Systems / Ratasich, D., Höftberger, O., Isakovic, H., Shafique, M., & Grosu, R. (2017). A Self-Healing Framework for Building Resilient Cyber-Physical Systems. In 2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC). 20th IEEE International Symposium on Real-Time Computing (ISORC 2017), Toronto, Canada, Non-EU. IEEE. https://doi.org/10.1109/isorc.2017.7
• A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study / Andjelkovic, M., Krstic, M., Kraemer, R., Veeravalli, V. S., & Steininger, A. (2017). A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. In Proceedings of the 26th IEEE Asian Test Symposium (ATS´17) (pp. 1–6). http://hdl.handle.net/20.500.12708/57265
• Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap / Shafique, M., Hafiz, R., Javed, M. U., Abbas, S., Sekanina, L., Vasicek, Z., & Mrazek, V. (2017). Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. In 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI’17), 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI’17), EU. IEEE. https://doi.org/10.1109/isvlsi.2017.124
• Low-overhead Aging-aware Resource Management on Embedded GPUs / Lee, H., Shafique, M., & Al Faruque, M. A. (2017). Low-overhead Aging-aware Resource Management on Embedded GPUs. In Proceedings of the 54th Annual Design Automation Conference 2017. 2017 ACM/EDAC/IEEE 54th Design Automation Conference (DAC’17), Austin, Texas, USA, Non-EU. ACM. https://doi.org/10.1145/3061639.3062277
• QuAd / Hanif, M. A., Hafiz, R., Hasan, O., & Shafique, M. (2017). QuAd. In Proceedings of the 54th Annual Design Automation Conference 2017. 2017 ACM/EDAC/IEEE 54th Design Automation Conference (DAC’17), Austin, Texas, USA, Non-EU. ACM. https://doi.org/10.1145/3061639.3062306
• Statistical Error Analysis for Low Power Approximate Adders / Ayub, M. K., Hasan, O., & Shafique, M. (2017). Statistical Error Analysis for Low Power Approximate Adders. In Proceedings of the 54th Annual Design Automation Conference 2017. 2017 ACM/EDAC/IEEE 54th Design Automation Conference (DAC’17), Austin, Texas, USA, Non-EU. ACM. https://doi.org/10.1145/3061639.3062319
• Embracing approximate computing for energy-efficient motion estimation in high efficiency video coding / El-Harouni, W., Rehman, S., Prabakaran, B. S., Kumar, A., Hafiz, R., & Shafique, M. (2017). Embracing approximate computing for energy-efficient motion estimation in high efficiency video coding. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017 IEEE/ACM 20th Design, Automation and Test in Europe Conference (DATE’17), Lausanne, Switzerland, EU. IEEE. https://doi.org/10.23919/date.2017.7927209
• Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores / Subramaniyan, A., Rehman, S., Shafique, M., Kumar, A., & Henkel, J. (2017). Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017 IEEE/ACM 20th Design, Automation and Test in Europe Conference (DATE’17), Lausanne, Switzerland, EU. IEEE. https://doi.org/10.23919/date.2017.7926955
• Scalable probabilistic power budgeting for many-cores / Pathania, A., Khdr, H., Shafique, M., Mitra, T., & Henkel, J. (2017). Scalable probabilistic power budgeting for many-cores. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017 IEEE/ACM 20th Design, Automation and Test in Europe Conference (DATE’17), Lausanne, Switzerland, EU. IEEE. https://doi.org/10.23919/date.2017.7927108
• CAnDy-TM: Comparative analysis of dynamic thermal management in many-cores using model checking / Bukhari, S. A. A., Lodhi, F. K., Hasan, O., Shafique, M., & Henkel, J. (2017). CAnDy-TM: Comparative analysis of dynamic thermal management in many-cores using model checking. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017 IEEE/ACM 20th Design, Automation and Test in Europe Conference (DATE’17), Lausanne, Switzerland, EU. IEEE. https://doi.org/10.23919/date.2017.7927191
• Secure Cyber-Physical Systems: Current trends, tools and open research problems / Chattopadhyay, A., Prakash, A., & Shafique, M. (2017). Secure Cyber-Physical Systems: Current trends, tools and open research problems. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. 2017 IEEE/ACM 20th Design, Automation and Test in Europe Conference (DATE’17), Lausanne, Switzerland, EU. IEEE. https://doi.org/10.23919/date.2017.7927154
• On Linear-Time Data Dissemination in Dynamic Rooted Trees / Zeiner, M., Schmid, U., & Schwarz, M. (2017). On Linear-Time Data Dissemination in Dynamic Rooted Trees. In 19th ÖMG Congress and Annual DMV Meetig Program and Books of Abstracts (p. 87). http://hdl.handle.net/20.500.12708/57124
• Measuring metastability using a time-to-digital converter / Polzer, T., Huemer, F., & Steininger, A. (2017). Measuring metastability using a time-to-digital converter. In 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Dresden, EU. IEEE Service Center. https://doi.org/10.1109/ddecs.2017.7934582
• Measuring Metastability with Free-Running Clocks / Najvirt, R., Polzer, T., & Steininger, A. (2017). Measuring Metastability with Free-Running Clocks. In 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California, Non-EU. IEEE Computer Society. https://doi.org/10.1109/async.2017.18
• A short counterexample property for safety and liveness verification of fault-tolerant distributed algorithms / Konnov, I., Lazić, M., Veith, H., & Widder, J. (2017). A short counterexample property for safety and liveness verification of fault-tolerant distributed algorithms. In Proceedings of the 44th ACM SIGPLAN Symposium on Principles of Programming Languages. 44th ACM SIGPLAN Symposium on Principles of Programming Languages (POPL), Paris, France, EU. ACM. https://doi.org/10.1145/3009837.3009860
• Metastability Tolerant Computing / Tarawneh, G., Függer, M., & Lenzen, C. (2017). Metastability Tolerant Computing. In 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California, Non-EU. IEEE Computer Society. https://doi.org/10.1109/async.2017.9
• Brief Announcement: Lower Bounds for Asymptotic Consensus in Dynamic Networks / Függer, M., Nowak, T., & Schwarz, M. (2017). Brief Announcement: Lower Bounds for Asymptotic Consensus in Dynamic Networks. In Leibniz International Proceedings in Informatics (LIPIcs) (p. 3). https://doi.org/10.4230/LIPIcs.DISC.2017.51
• Metastability-Aware Memory-Efficient Time-to-Digital Converters / Függer, M., Kinali, A., Lenzen, C., & Polzer, T. (2017). Metastability-Aware Memory-Efficient Time-to-Digital Converters. In 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California, Non-EU. IEEE Computer Society. https://doi.org/10.1109/async.2017.12
• Design Space Exploration and Run-Time Adaptation for Multicore Resource Management Under Performance and Power Constraints / Pagani, S., Shafique, M., & Henkel, J. (2017). Design Space Exploration and Run-Time Adaptation for Multicore Resource Management Under Performance and Power Constraints. In Handbook of Hardware/Software Codesign (pp. 301–332). Springer Science+Business Media. https://doi.org/10.1007/978-94-017-7267-9_11
• Thermal Safe Power: Efficient Thermal-Aware Power Budgeting for Manycore Systems in Dark Silicon / Pagani, S., Khdr, H., Chen, J.-J., Shafique, M., Li, M., & Henkel, J. (2017). Thermal Safe Power: Efficient Thermal-Aware Power Budgeting for Manycore Systems in Dark Silicon. In The Dark Side of Silicon (pp. 125–158). Springer International Publishing. https://doi.org/10.1007/978-3-319-31596-6_5
• Adroit Use of Dark Silicon for Power, Performance and Reliability Optimisation of NoCs / Bokhari, H., Shafique, M., Henkel, J., & Parameswaran, S. (2017). Adroit Use of Dark Silicon for Power, Performance and Reliability Optimisation of NoCs. In The Dark Side of Silicon (pp. 291–325). Springer International Publishing. https://doi.org/10.1007/978-3-319-31596-6_11
• Energy Efficient Embedded Video Processing Systems / Khan, M. U. K., Shafique, M., & Henkel, J. (2017). Energy Efficient Embedded Video Processing Systems. Springer International Publishing. https://doi.org/10.1007/978-3-319-61455-7

2016

• Unfaithful Glitch Propagation in Existing Binary Circuit Models / Függer, M., Nowak, T., & Schmid, U. (2016). Unfaithful Glitch Propagation in Existing Binary Circuit Models. IEEE Transactions on Computers, 65(3), 964–978. https://doi.org/10.1109/tc.2015.2435791
• FWF-Proposal SPRG: Structural Properties of Random Graphs / Zeiner, M., Schmid, U., Schilcher, U., & Bettstetter, C. (2016). FWF-Proposal SPRG: Structural Properties of Random Graphs. http://hdl.handle.net/20.500.12708/39096
• Gracefully Degrading Consensus and k-Set Agreement in Directed Dynamic Networks / Biely, M., Robinson, P., Schmid, U., Schwarz, M., & Winkler, K. (2016). Gracefully Degrading Consensus and k-Set Agreement in Directed Dynamic Networks (TUW-258404). http://hdl.handle.net/20.500.12708/39151
• Fast, Robust, Quantizable Approximate Consensus / Charron-Bost, B., Függer, M., & Nowak, T. (2016). Fast, Robust, Quantizable Approximate Consensus. In I. Chatzigiannakis, M. Mitzenmacher, Y. Rabani, & D. Sangiorgi (Eds.), Proceedings 43rd International Colloquium on Automata, Languages, and Programming (ICALP’16) (pp. 137:1-137:14). Leibniz International Proceedings in Informatics (LIPIcs). https://doi.org/10.4230/LIPIcs.ICALP.2016.137
• Decidability of Parameterized Verification / Bloem, R., Jacobs, S., Khalimov, A., Konnov, I., Rubin, S., Veith, H., & Widder, J. (2016). Decidability of Parameterized Verification. ACM SIGACT News, 47(2), 53–64. https://doi.org/10.1145/2951860.2951873
• Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity / Chen, K.-H., Chen, J.-J., Kriebel, F., Rehman, S., Shafique, M., & Henkel, J. (2016). Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity. IEEE Transactions on Computers, 65(11), 3441–3455. https://doi.org/10.1109/tc.2016.2532862
• Content-Aware Low-Power Configurable Aging Mitigation for SRAM Memories / Shafique, M., Khan, M. U. K., & Henkel, J. (2016). Content-Aware Low-Power Configurable Aging Mitigation for SRAM Memories. IEEE Transactions on Computers, 65(12), 3617–3630. https://doi.org/10.1109/tc.2016.2553025
• HEX: Scaling Honeycombs is Easier than Scaling Clock Trees / Dolev, D., Függer, M., Lenzen, C., Perner, M., & Schmid, U. (2016). HEX: Scaling Honeycombs is Easier than Scaling Clock Trees. Journal of Computer and System Sciences, 82(5), 929–956. https://doi.org/10.1016/j.jcss.2016.03.001
• Scalable Power Management for On-Chip Systems with Malleable Applications / Shafique, M., Ivanov, A., Vogel, B., & Henkel, J. (2016). Scalable Power Management for On-Chip Systems with Malleable Applications. IEEE Transactions on Computers, 65(11), 3398–3412. https://doi.org/10.1109/tc.2016.2540631
• Easy Impossibility Proofs for k-Set Agreement / Schmid, U. (2016). Easy Impossibility Proofs for k-Set Agreement. Dagstuhl Seminar #16282 Topological Methods in Distributed Computing, Wadern, Germany. https://doi.org/10.4230/DagRep.6.7.31
• Power and Thermal Management in Massive Multicore Chips: Theoretical Foundation meets Architectural Innovation and Resource Allocation / Bogdan, P., Pande, P. P., Amrouch, H., Shafique, M., & Henkel, J. (2016). Power and Thermal Management in Massive Multicore Chips: Theoretical Foundation meets Architectural Innovation and Resource Allocation. In CASES (pp. 1–2). ACM. https://doi.org/10.1145/2968455.2974013
• Reconciling Fault-Tolerance and Robustness ? / Schmid, U. (2016). Reconciling Fault-Tolerance and Robustness ? Workshop on Design and Analysis of Robust Systems @ CPS-Week 2016, Hofburg Vienna, Austria, Austria. http://hdl.handle.net/20.500.12708/86399
• Model Checking of Threshold-based Fault-Tolerant Distributed Algorithms / Lazić, M., Konnov, I., Veith, H., & Widder, J. (2016). Model Checking of Threshold-based Fault-Tolerant Distributed Algorithms. 7th Workshop on Program Semantics, Specification and Verification: Theory and Applications, St. Petersburg, Russia, Non-EU. http://hdl.handle.net/20.500.12708/86426
• Parameterized Verification of Liveness of Distributed Algorithms / Konnov, I., Lazić, M., Veith, H., & Widder, J. (2016). Parameterized Verification of Liveness of Distributed Algorithms. Workshop on Formal Reasoning in Distributed Algorithms (FRiDA), Wien, Austria. http://hdl.handle.net/20.500.12708/86425
• Broadcasting in Random Trees / Zeiner, M., Schwarz, M., Winkler, K., & Schmid, U. (2016). Broadcasting in Random Trees. ALEA in Europe - Young Researchers Workshop, TU Wien, Austria. http://hdl.handle.net/20.500.12708/86332
• Fault-Tolerant Clock Synchronization with High Precision / Kinali, A., Huemer, F., & Lenzen, C. (2016). Fault-Tolerant Clock Synchronization with High Precision. In 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2016 IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA, Non-EU. https://doi.org/10.1109/isvlsi.2016.88
• A General Approach for Comparing Metastable Behavior of Digital CMOS Gates / Polzer, T., & Steininger, A. (2016). A General Approach for Comparing Metastable Behavior of Digital CMOS Gates. In Proc 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). http://hdl.handle.net/20.500.12708/56886
• Study of a Delayed Single-Event Effect in the Muller C-element / Veeravalli, V. S., & Steininger, A. (2016). Study of a Delayed Single-Event Effect in the Muller C-element. In Proc 21st IEEE European Test Symposium. 21st IEEE European Test Symposium, Amsterdam, EU. http://hdl.handle.net/20.500.12708/56885
  Project: EASET (2014–2017)
• Design and Physical Implementation of a Target ASIC for SET Experiments / Veeravalli, V. S., & Steininger, A. (2016). Design and Physical Implementation of a Target ASIC for SET Experiments. In Proc. 2016 Euromicro Conference on Digital System Design (DSD) (pp. 694–697). IEEE. http://hdl.handle.net/20.500.12708/56884
  Project: EASET (2014–2017)
• A Programmable Delay Line for Metastability Characterization in FPGAs / Polzer, T., Huemer, F., & Steininger, A. (2016). A Programmable Delay Line for Metastability Characterization in FPGAs. In Proceedings 24th Austrian Workshop on Microelectronics (p. 6). http://hdl.handle.net/20.500.12708/56883
• A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes / Huemer, F., Lechner, J., & Steininger, A. (2016). A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes. In Proceedings 2016 IEEE International Conference on Computer Design (pp. 392–395). http://hdl.handle.net/20.500.12708/56881
• Architectural-space exploration of approximate multipliers / Rehman, S., El-Harouni, W., Shafique, M., Kumar, A., & Henkel, J. (2016). Architectural-space exploration of approximate multipliers. In Proceedings of the 35th International Conference on Computer-Aided Design. The IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Non-EU. ACM New York, NY, USA. https://doi.org/10.1145/2966986.2967005
• A Framework for Connectivity Monitoring in Wireless Sensor Networks / Pfleger, D., & Schmid, U. (2016). A Framework for Connectivity Monitoring in Wireless Sensor Networks. In Proceedings 10th International Conference on Sensor Technlogies and Applications (SENSORCOMM’16) (pp. 40–48). IARIA XPS Press. http://hdl.handle.net/20.500.12708/56746
• Fast consensus under eventually stabilizing message adversaries / Schwarz, M., Winkler, K., & Schmid, U. (2016). Fast consensus under eventually stabilizing message adversaries. In Proceedings of the 17th International Conference on Distributed Computing and Networking. 17th International Conference on Distributed Computing and Networking, Singapore, Non-EU. ACM. https://doi.org/10.1145/2833312.2833323
• Fifty Shades of Synchrony / Steininger, A. (2016). Fifty Shades of Synchrony. In A. Mokhov (Ed.), This Asynchronous Woirld (pp. 294–300). Newcastle University. http://hdl.handle.net/20.500.12708/29323

2015

• Gracefully Degrading Consensus and k-Set Agreement in Directed Dynamic Networks / Biely, M., Robinson, P., Schmid, U., Schwarz, M., & Winkler, K. (2015). Gracefully Degrading Consensus and k-Set Agreement in Directed Dynamic Networks. In Lecture Notes in Computer Science. The international Conference on NETworked sYStems, Agadir, Marokko, Non-EU. Springer LNCS. https://doi.org/10.1007/978-3-319-26850-7
• On the Appropriate Handling of Metastable Voltages in FPGAs / Polzer, T., Najvirt, R., Beck, F., & Steininger, A. (2015). On the Appropriate Handling of Metastable Voltages in FPGAs. Journal of Circuits, Systems, and Computers, 25(03), 1640020. https://doi.org/10.1142/s021812661640020x
• Time Complexity of Link Reversal Routing / Charron-Bost, B., Függer, M., Welch, J. L., & Widder, J. (2015). Time Complexity of Link Reversal Routing. ACM Transactions on Algorithms, 11(3), 1–39. https://doi.org/10.1145/2644815
• Building reliable systems-on-chip in nanoscale technologies / Steininger, A., Zimmermann, H., Jantsch, A., Hofbauer, M., Schmid, U., Schweiger, K., & Savulimedu Veeravalli, V. (2015). Building reliable systems-on-chip in nanoscale technologies. Elektrotechnik Und Informationstechnik, 132(6), 301–306. https://doi.org/10.1007/s00502-015-0319-0
• The effect of forgetting on the performance of a synchronizer / Függer, M., Kößler, A., Nowak, T., Schmid, U., & Zeiner, M. (2015). The effect of forgetting on the performance of a synchronizer. Performance Evaluation, 93, 1–16. https://doi.org/10.1016/j.peva.2015.08.002
• A Composable Real-Time Architecture for Replicated Railway Applications / Resch, S., Steininger, A., & Scherrer, C. (2015). A Composable Real-Time Architecture for Replicated Railway Applications. The Journal of Systems Architecture: Embedded Software Design, 61(9), 472–485. https://doi.org/10.1016/j.sysarc.2015.04.003
• Fault-tolerant Distributed Systems in Hardware / Dolev, D., Függer, M., Lenzen, C., Schmid, U., & Steininger, A. (2015). Fault-tolerant Distributed Systems in Hardware. Bulletin of the EATCS, 2(116), 43. http://hdl.handle.net/20.500.12708/151760
• Optimal Strategies for Repeated Leader Election / Zeiner, M., Függer, M., Nowak, T., & Schmid, U. (2015). Optimal Strategies for Repeated Leader Election. Joint Austrian-Hungarian Mathematical Conference 2015, Györ, EU. http://hdl.handle.net/20.500.12708/86086
• Experimental Validation of a Faithful Binary Circuit Model / Najvirt, R., Függer, M., Nowak, T., Schmid, U., Hofbauer, M., & Schweiger, K. (2015). Experimental Validation of a Faithful Binary Circuit Model. In Proceedings of the 25th edition on Great Lakes Symposium on VLSI. Great Lakes Symposium on VLSI (GLSVLSI’15), Pittsburgh, Pennsylvania, USA, Non-EU. https://doi.org/10.1145/2742060.2742081
• A Versatile and Reliable Glitch Filter for Clocks / Najvirt, R., & Steininger, A. (2015). A Versatile and Reliable Glitch Filter for Clocks. In 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (p. 8). http://hdl.handle.net/20.500.12708/56360
• Can we trust SET Injection Models? / Veeravalli, V. S., & Steininger, A. (2015). Can we trust SET Injection Models? In MEDIAN Finale Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (p. 6). http://hdl.handle.net/20.500.12708/56359
• Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes / Lechner, J., Steininger, A., & Huemer, F. (2015). Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes. In 33rd IEEE International Conference on Computer Design (p. 8). http://hdl.handle.net/20.500.12708/56358
• A Pausible Clock with Crystal Oscillator Accuracy / Najvirt, R., & Steininger, A. (2015). A Pausible Clock with Crystal Oscillator Accuracy. In 22nd European Conference on Circuit Theory and Design (p. 4). http://hdl.handle.net/20.500.12708/56356
• Reliable and Continuous Measurement of SET Pulse Widths / Veeravalli, V. S., & Steininger, A. (2015). Reliable and Continuous Measurement of SET Pulse Widths. In 18th Euromicro Conference on Digital System Design (p. 8). http://hdl.handle.net/20.500.12708/56354
• Enhanced Metastability Characterization based on AC Analysis / Polzer, T., & Steininger, A. (2015). Enhanced Metastability Characterization based on AC Analysis. In 18th Euromicro Conference on Digital System Design (p. 9). http://hdl.handle.net/20.500.12708/56353
• Measuring the Distribution of Metastable Upsets over Time / Polzer, T., & Steininger, A. (2015). Measuring the Distribution of Metastable Upsets over Time. In Measuring the Distribution of Metastable Upsets over Time (p. 8). http://hdl.handle.net/20.500.12708/56352
• Containment of Metastable Voltages in FPGAs / Najvirt, R., Polzer, T., Beck, F., & Steininger, A. (2015). Containment of Metastable Voltages in FPGAs. In 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). http://hdl.handle.net/20.500.12708/56351
• Revisiting Sorting Network based Completion Detection for 4 Phase Delay Insensitive Codes / Huemer, F., Schütz, M., & Steininger, A. (2015). Revisiting Sorting Network based Completion Detection for 4 Phase Delay Insensitive Codes. In Austrochip Workshop on Microelectronics (p. 6). http://hdl.handle.net/20.500.12708/56350
• A Practical Comparison of 2-Phase Delay Insensitve Communication Protocols / Schütz, M., Huemer, F., & Steininger, A. (2015). A Practical Comparison of 2-Phase Delay Insensitve Communication Protocols. In Austrochip Workshop on Microelectronics (p. 6). http://hdl.handle.net/20.500.12708/56349
• How to Synchronize a Pausible Clock to a Reference / Najvirt, R., & Steininger, A. (2015). How to Synchronize a Pausible Clock to a Reference. In 21st IEEE International Symposium on Asynchronous Circuits and Systems (p. 8). http://hdl.handle.net/20.500.12708/56348
• Towards binary circuit models that faithfully capture physical solvability / Függer, M., Najvirt, R., Nowak, T., & Schmid, U. (2015). Towards binary circuit models that faithfully capture physical solvability. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE’15) (pp. 1455–1460). http://hdl.handle.net/20.500.12708/56310
• SMT and POR Beat Counter Abstraction: Parameterized Model Checking of Threshold-Based Distributed Algorithms / Konnov, I., Veith, H., & Widder, J. (2015). SMT and POR Beat Counter Abstraction: Parameterized Model Checking of Threshold-Based Distributed Algorithms. In Computer Aided Verification (pp. 85–102). LNCS Springer. https://doi.org/10.1007/978-3-319-21690-4_6
• A Framework for Connectivity Monitoring in Wireless Sensor Networks / Pfleger, D., & Schmid, U. (2015). A Framework for Connectivity Monitoring in Wireless Sensor Networks (TUW-241107). http://hdl.handle.net/20.500.12708/38487
• Fast Consensus under Eventually Stabilizing Message Adversaries / Schwarz, M., Winkler, K., & Schmid, U. (2015). Fast Consensus under Eventually Stabilizing Message Adversaries (TUW-240061). http://hdl.handle.net/20.500.12708/38462
• Decidability of Parameterized Verification / Bloem, R., Jacobs, S., Khalimov, A., Konnov, I., Rubin, S., Veith, H., & Widder, J. (2015). Decidability of Parameterized Verification. In Synthesis Lectures on Distributed Computing Theory (p. 170). Morgan & Claypool Publishers. https://doi.org/10.2200/s00658ed1v01y201508dct013

2014

• Runtime verification of microcontroller binary code / Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., & Kowalewski, S. (2014). Runtime verification of microcontroller binary code. Science of Computer Programming, 80, 109–129. https://doi.org/10.1016/j.scico.2012.10.015
• The Generalized Loneliness Detector and Weak System Models for k-Set Agreement / Biely, M., Robinson, P., & Schmid, U. (2014). The Generalized Loneliness Detector and Weak System Models for k-Set Agreement. IEEE Transactions on Parallel and Distributed Systems, 25(4), 1078–1088. https://doi.org/10.1109/tpds.2013.77
• Brief announcement / Schwarz, M., Winkler, K., Schmid, U., Biely, M., & Robinson, P. (2014). Brief announcement. In Proceedings of the 2014 ACM symposium on Principles of distributed computing - PODC ’14. 33th ACM SIGACTSIGOPS Symposium on Principles of Distributed Computing (PODC), Paris, France, EU. ACM. https://doi.org/10.1145/2611462.2611506
• Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip / Dolev, D., Függer, M., Posch, M., Schmid, U., Steininger, A., & Lenzen, C. (2014). Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip. Journal of Computer and System Sciences, 80(4), 860–900. https://doi.org/10.1016/j.jcss.2014.01.001
• On a family of $q$-binomial distributions / Zeiner, M. (2014). On a family of $q$-binomial distributions. Mathematica Slovaca, 64(2), 479–510. https://doi.org/10.2478/s12175-014-0220-z
• Reconciling fault-tolerant distributed algorithms and real-time computing / Moser, H., & Schmid, U. (2014). Reconciling fault-tolerant distributed algorithms and real-time computing. Distributed Computing, 27(3), 203–230. https://doi.org/10.1007/s00446-013-0204-1
• Fault-tolerant Algorithms for Tick-generation in Asynchronous Logic: Robust Pulse Generation / Dolev, D., Függer, M., Schmid, U., & Lenzen, C. (2014). Fault-tolerant Algorithms for Tick-generation in Asynchronous Logic: Robust Pulse Generation. Journal of the ACM, 61(5), 1–74. https://doi.org/10.1145/2560561
• A Framework for Automated Competitive Analysis of On-line Scheduling of Firm-Deadline Tasks / Pavlogiannis, A., Chatterjee, K., Schmid, U., & Kößler, A. (2014). A Framework for Automated Competitive Analysis of On-line Scheduling of Firm-Deadline Tasks. In 2014 IEEE Real-Time Systems Symposium. 35th IEEE Real-Time Systems Symposium, Rome, EU. https://doi.org/10.1109/rtss.2014.9
• Equivalence of clock gating and synchronization with applicability to GALS communication / Najvirt, R., & Steininger, A. (2014). Equivalence of clock gating and synchronization with applicability to GALS communication. In 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, Isles Balears, Spain, EU. IEEE. https://doi.org/10.1109/patmos.2014.6951873
• Long term on-chip monitoring of SET pulsewidths in a fully digital ASIC / Veeravalli, V. S., & Steininger, A. (2014). Long term on-chip monitoring of SET pulsewidths in a fully digital ASIC. In 22nd Austrian Workshop on Microelectronics (Austrochip). 22nd Austrian Workshop on Microelectronics, Graz, Austria. IEEE. https://doi.org/10.1109/austrochip.2014.6946318
  Project: EASET (2014–2017)
• Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example / Steininger, A., Veeravalli, V. S., Alexandrescu, D., Costenaro, E., & Anghel, L. (2014). Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. In 2014 IEEE 32nd International Conference on Computer Design (ICCD). 2014 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea, Non-EU. IEEE. https://doi.org/10.1109/iccd.2014.6974663
  Project: EASET (2014–2017)
• A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments / Naqvi, S. R., & Steininger, A. (2014). A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments. In Proceedings Design Automation &Test in Europe (p. 6). http://hdl.handle.net/20.500.12708/55132
• Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum / Anghel, L., Veeravalli, V. S., Alexandrescu, D., Steininger, A., Schneider, K., & Costenaro, E. (2014). Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum. In Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10) (p. 6). http://hdl.handle.net/20.500.12708/55131
• Diagnosis of SET Propagation in Combinational Logic under Dynamic Operation / Veeravalli, V. S., & Steininger, A. (2014). Diagnosis of SET Propagation in Combinational Logic under Dynamic Operation. In Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10) (p. 6). http://hdl.handle.net/20.500.12708/55130
• Architecture for monitoring SET propagation in 16-bit Sklansky adder / Veeravalli, V. S., & Steininger, A. (2014). Architecture for monitoring SET propagation in 16-bit Sklansky adder. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA, Non-EU. https://doi.org/10.1109/isqed.2014.6783354
• Measuring SET pulsewidths in logic gates using digital infrastructure / Veeravalli, V. S., Steininger, A., & Schmid, U. (2014). Measuring SET pulsewidths in logic gates using digital infrastructure. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA, Non-EU. https://doi.org/10.1109/isqed.2014.6783331
• Protection of Muller-Pipelines from transient faults / Naqvi, S. R., Lechner, J., & Steininger, A. (2014). Protection of Muller-Pipelines from transient faults. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA, Non-EU. https://doi.org/10.1109/isqed.2014.6783315
• FWF-Proposal ADynNet: Gracefully Degrading Agreement in Directed Dynamic Networks / Schmid, U. (2014). FWF-Proposal ADynNet: Gracefully Degrading Agreement in Directed Dynamic Networks (TUW-235381). http://hdl.handle.net/20.500.12708/38308
• Final Report FWF FATAL-Project (P21694) / Schmid, U. (2014). Final Report FWF FATAL-Project (P21694) (TUW-235380). http://hdl.handle.net/20.500.12708/38307
• Tutorial on Parameterized Model Checking of Fault-Tolerant Distributed Algorithms / Gmeiner, A., Konnov, I., Schmid, U., Veith, H., & Widder, J. (2014). Tutorial on Parameterized Model Checking of Fault-Tolerant Distributed Algorithms. In Lecture Notes in Computer Science (pp. 122–171). Springer. https://doi.org/10.1007/978-3-319-07317-0_4

2013

• FATAL+HEX: Fault-Tolerant Self-Stabilizing Clock Generation+Distribution / Dolev, D., Függer, M., Hofstätter, M., Lenzen, C., Perner, M., Posch, M., Schmid, U., Sigl, M., & Steininger, A. (2013). FATAL+HEX: Fault-Tolerant Self-Stabilizing Clock Generation+Distribution. Poster Session at the CSAIL Industry Affiliates Program (CSAIL-IAP) Annual Meeting, Cambridge, MA, USA, Non-EU. http://hdl.handle.net/20.500.12708/85710
• Gracefully Degrading Consensus and k-set Agreement under Dynamic Link Failures / Schwarz, M., Winkler, K., Schmid, U., Biely, M., & Robinson, P. (2013). Gracefully Degrading Consensus and k-set Agreement under Dynamic Link Failures (TUW-220473). http://hdl.handle.net/20.500.12708/37755
• Supply Voltage Dependent On-Chip Single-Event Transient Pulse Shape Measurements in 90-nm Bulk CMOS Under Alpha Irradiation / Hofbauer, M., Schweiger, K., Zimmermann, H., Giesen, U., Langner, F., Schmid, U., & Steininger, A. (2013). Supply Voltage Dependent On-Chip Single-Event Transient Pulse Shape Measurements in 90-nm Bulk CMOS Under Alpha Irradiation. IEEE Transactions on Nuclear Science, 60(4), 2640–2646. http://hdl.handle.net/20.500.12708/156043
• An infrastructure for accurate characterization of single-event transients in digital circuits / Veeravalli, V. S., Polzer, T., Schmid, U., Steininger, A., Hofbauer, M., Schweiger, K., Dietrich, H., Schneider-Hornstein, K., Zimmermann, H., Voss, K.-O., Merk, B., & Hajek, M. (2013). An infrastructure for accurate characterization of single-event transients in digital circuits. Microprocessors and Microsystems, 37, 772–791. http://hdl.handle.net/20.500.12708/156041
• On the performance of a retransmission-based synchronizer / Nowak, T., Függer, M., & Kößler, A. (2013). On the performance of a retransmission-based synchronizer. Theoretical Computer Science, 509, 25–39. https://doi.org/10.1016/j.tcs.2012.04.035
• Runtime verification of embedded real-time systems / Reinbacher, T., Függer, M., & Brauer, J. (2013). Runtime verification of embedded real-time systems. Formal Methods in System Design, 44(3), 203–239. https://doi.org/10.1007/s10703-013-0199-z
  Project: CEVTES (2010–2013)
• The Effect of Forgetting on the Performance of a Synchronizer / Zeiner, M., Függer, M., Schmid, U., Kößler, A., & Nowak, T. (2013). The Effect of Forgetting on the Performance of a Synchronizer. 18th ÖMG Congress and Annual DMV Meeting, Universität Innsbruck, Austria. http://hdl.handle.net/20.500.12708/85720
• Single Event Transient Pulse Shape Measurements by On-chip Sense Amplifiers in a Single Inverter for Intermediate Input States under Alpha Particle Irradiation / Hofbauer, M., Schweiger, K., Gaberl, W., Zimmermann, H., Giesen, U., Langner, F., Schmid, U., & Steininger, A. (2013). Single Event Transient Pulse Shape Measurements by On-chip Sense Amplifiers in a Single Inverter for Intermediate Input States under Alpha Particle Irradiation. IEEE Nuclear and Space Radiation Effects Conference (NSREC), San Francisco, California (USA), Non-EU. http://hdl.handle.net/20.500.12708/85741
• Automated Analysis of Real-Time Scheduling using Graph Games / Chatterjee, K., Kößler, A., & Schmid, U. (2013). Automated Analysis of Real-Time Scheduling using Graph Games. In Proceedings 16th ACM International Conference on Hybrid Systems: Computation and Control (HSCC’13) (pp. 163–172). ACM. http://hdl.handle.net/20.500.12708/55031
• Digital Late-Transition Metastability Simulation Model / Polzer, T., & Steininger, A. (2013). Digital Late-Transition Metastability Simulation Model. In Proceedings of the 16th Euromicro Conference on Digital System Design (p. 8). http://hdl.handle.net/20.500.12708/55024
• Metastability Characterization for Muller C-Elements / Polzer, T., & Steininger, A. (2013). Metastability Characterization for Muller C-Elements. In 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013) (p. 8). http://hdl.handle.net/20.500.12708/55023
• An Approach for Efficient Metastability Characterization of FPGAs through the Designer / Polzer, T., & Steininger, A. (2013). An Approach for Efficient Metastability Characterization of FPGAs through the Designer. In 19th IEEE International Symposium on Asynchronous Circuits and Systems (p. 9). http://hdl.handle.net/20.500.12708/55021
• A Multi-Credit Flow Control Scheme for Asynchronous NoCs / Naqvi, S. R., Najvirt, R., & Steininger, A. (2013). A Multi-Credit Flow Control Scheme for Asynchronous NoCs. In Proc. 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). http://hdl.handle.net/20.500.12708/55006
• Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs / Najvirt, R., Naqvi, S. R., & Steininger, A. (2013). Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. In Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on (p. 9). http://hdl.handle.net/20.500.12708/55005
• Particle Strikes in C-Gates: Relevance of SET Shapes / Najvirt, R., Veeravalli, V. S., & Steininger, A. (2013). Particle Strikes in C-Gates: Relevance of SET Shapes. In Proceedings of the MEDIAN Workshop 2013 (p. 4). http://hdl.handle.net/20.500.12708/55003
• Performance of Radiation Hardening Techniques under Voltage and Temperature Variations / Veeravalli, V. S., & Steininger, A. (2013). Performance of Radiation Hardening Techniques under Voltage and Temperature Variations. In Proc. 2013 IEEE Aerospace Conference (p. 6). http://hdl.handle.net/20.500.12708/55004
• Software Composability and Mixed Criticality for Triple Modular Redundant Architectures / Resch, S., Steininger, A., & Scherrer, C. (2013). Software Composability and Mixed Criticality for Triple Modular Redundant Architectures. In Proceedings of the 2013 SASSUR Workshop (p. 4). http://hdl.handle.net/20.500.12708/55002
• An SET Tolerant Tree Arbiter Cell / Naqvi, S. R., Steininger, A., & Lechner, J. (2013). An SET Tolerant Tree Arbiter Cell. In Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on (p. 9). http://hdl.handle.net/20.500.12708/55001
• SET Propagation in Micropipelines / Polzer, T., & Steininger, A. (2013). SET Propagation in Micropipelines. In 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013) (p. 8). http://hdl.handle.net/20.500.12708/54998
• Unfaithful Glitch Propagation in Existing Binary Circuit Models / Függer, M., Nowak, T., & Schmid, U. (2013). Unfaithful Glitch Propagation in Existing Binary Circuit Models. In 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems. 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, CA, Non-EU. https://doi.org/10.1109/async.2013.9
• Transience Bounds for Distributed Algorithms / Charron-Bost, B., Függer, M., & Nowak, T. (2013). Transience Bounds for Distributed Algorithms. In Lecture Notes in Computer Science (pp. 77–90). Lecture Notes in Computer Science. https://doi.org/10.1007/978-3-642-40229-6_6
• Efficient Construction of Global Time in SoCs Despite Arbitrary Faults / Lenzen, C., Függer, M., Hofstätter, M., & Schmid, U. (2013). Efficient Construction of Global Time in SoCs Despite Arbitrary Faults. In 2013 Euromicro Conference on Digital System Design. 16th Euromicro Conference on Digital System Design (DSD 2013), Santander, Spain, EU. Digital System Design (DSD), 2013 Euromicro Conference on. https://doi.org/10.1109/dsd.2013.97
• Byzantine Self-Stabilizing Clock Distribution with HEX: Implementation, Simulation, Clock Multiplication / Perner, M., Schmid, U., Lenzen, C., & Sigl, M. (2013). Byzantine Self-Stabilizing Clock Distribution with HEX: Implementation, Simulation, Clock Multiplication. In Proceedings of the 6th IARA International Conference on Dependability (DEPEND’13) (pp. 6–15). IARA. http://hdl.handle.net/20.500.12708/54927
• The Effect of Forgetting on the Performance of a Synchronizer / Függer, M., Kößler, A., Nowak, T., Schmid, U., & Zeiner, M. (2013). The Effect of Forgetting on the Performance of a Synchronizer. In Algorithms for Sensor Systems (pp. 185–200). https://doi.org/10.1007/978-3-642-45346-5_14
• HEX / Dolev, D., Lenzen, C., Függer, M., Schmid, U., & Perner, M. (2013). HEX. In Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures. SPAA ’13, Montreal, Canada, Non-EU. ACM. https://doi.org/10.1145/2486159.2486192
• Brief announcement / John, A., Konnov, I., Schmid, U., Veith, H., & Widder, J. (2013). Brief announcement. In Proceedings of the 2013 ACM symposium on Principles of distributed computing - PODC ’13. ACM SIGACT-SIGOPS Symposium on Principles of Distributed Computing (PODC), Montreal, Kanada, Non-EU. ACM. https://doi.org/10.1145/2484239.2484285
• Parameterized model checking of fault-tolerant distributed algorithms by abstraction / John, A., Konnov, I., Schmid, U., Veith, H., & Widder, J. (2013). Parameterized model checking of fault-tolerant distributed algorithms by abstraction. In FMCAD (pp. 201–209). http://hdl.handle.net/20.500.12708/54827
• Towards Modeling and Model Checking Fault-Tolerant Distributed Algorithms / John, A., Konnov, I., Schmid, U., Veith, H., & Widder, J. (2013). Towards Modeling and Model Checking Fault-Tolerant Distributed Algorithms. In Model Checking Software (pp. 209–226). LNCS, Springer. https://doi.org/10.1007/978-3-642-39176-7_14
• Muller C-Element Metastability Containment / Polzer, T., Steininger, A., & Lechner, J. (2013). Muller C-Element Metastability Containment. In Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (pp. 103–112). Lecture Notes in Computer Science. http://hdl.handle.net/20.500.12708/54509
• A Generic Architecture for Robust Asynchronous Communication Links / Lechner, J., & Najvirt, R. (2013). A Generic Architecture for Robust Asynchronous Communication Links. In Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (pp. 121–130). Lecture Notes in Computer Science. http://hdl.handle.net/20.500.12708/54501
• Final Report FWF PSRTS-Project (P20529) / Schmid, U. (2013). Final Report FWF PSRTS-Project (P20529) (TUW-235379). http://hdl.handle.net/20.500.12708/38306

2012

• Reliable Gateway for Radiation Experiments on a VLSI Chip / Fritz, B., Veeravalli, V. S., & Steininger, A. (2012). Reliable Gateway for Radiation Experiments on a VLSI Chip. In Austrochip 2012 (pp. 65–70). http://hdl.handle.net/20.500.12708/54571
• Agreement in Directed Dynamic Networks / Biely, M., Robinson, P., & Schmid, U. (2012). Agreement in Directed Dynamic Networks. In Proceedings 19th International Colloquium on Structural Information and Communication Complexity (SIROCCO’12) (pp. 73–84). http://hdl.handle.net/20.500.12708/54563
• Consensus in the presence of mortal Byzantine faulty processes / Widder, J., Biely, M., Gridling, G., Weiss, B., & Blanquart, J.-P. (2012). Consensus in the presence of mortal Byzantine faulty processes. Distributed Computing, 24(6), 299–321. https://doi.org/10.1007/s00446-011-0147-3
• Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain / Hofbauer, M., Schweiger, K., Dietrich, H., Zimmermann, H., Voss, K.-O., Merk, B., Schmid, U., & Steininger, A. (2012). Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain. IEEE Transactions on Nuclear Science, 59(6), 2778–2784. https://doi.org/10.1109/tns.2012.2223233
• Reconciling fault-tolerant distributed computing and systems-on-chip / Függer, M., & Schmid, U. (2012). Reconciling fault-tolerant distributed computing and systems-on-chip. Distributed Computing, 24(6), 323–355. https://doi.org/10.1007/s00446-011-0151-7
• Single Event Effect Measurements in 90nm CMOS Circuits at the Microbeam Facility for the Project FATAL / Hofbauer, M., Schweiger, K., Dietrich, H., Zimmermann, H., Schmid, U., & Merk, B. (2012). Single Event Effect Measurements in 90nm CMOS Circuits at the Microbeam Facility for the Project FATAL. In GSI Scientific Report 2011 (p. 424). GSI Helmholtzzentrum für Schwerionenforschung GmbH. http://hdl.handle.net/20.500.12708/73103
• Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating through a 90 nm Bulk CMOS Inverter Chain / Hofbauer, M., Schweiger, K., Dietrich, H., Zimmermann, H., Voss, K. O., Merk, B., Schmid, U., & Steininger, A. (2012). Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating through a 90 nm Bulk CMOS Inverter Chain. Nuclear and Space Radiation Effects Conference (NSREC), Miami, FL, USA, Non-EU. http://hdl.handle.net/20.500.12708/89963
• Towards Self-stabilizing Byzantine Fault-Tolerant Clock Generation in Systems-on-Chip / Dolev, D., Függer, M., Lenzen, C., & Schmid, U. (2012). Towards Self-stabilizing Byzantine Fault-Tolerant Clock Generation in Systems-on-Chip. NITRD Workshop, Baltimore, USA, Non-EU. http://hdl.handle.net/20.500.12708/85536
• Who is afraid of Model Checking Distributed Algorithms? / John, A., Konnov, I., Schmid, U., Veith, H., & Widder, J. (2012). Who is afraid of Model Checking Distributed Algorithms? PUMA/RISE Seminar, Traunkirchen, Austria. http://hdl.handle.net/20.500.12708/85435
• Parameterized Model Checking of Fault-tolerant Distributed Algorithms / John, A., Konnov, I., Schmid, U., Veith, H., & Widder, J. (2012). Parameterized Model Checking of Fault-tolerant Distributed Algorithms. Dagstuhl Seminar 12461: Games and Decisions for Rigorous Systems Engineering, Dagstuhl, Deutschland, EU. http://hdl.handle.net/20.500.12708/85432
• Counter Attack against Byzantine Generals / John, A., Konnov, I., Schmid, U., Veith, H., & Widder, J. (2012). Counter Attack against Byzantine Generals. Alpine Verification Meeting, IST Austria, Austria. http://hdl.handle.net/20.500.12708/85359
• Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach / Milbredt, P., Glass, M., Lukasiewycz, M., Steininger, A., & Teich, J. (2012). Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach. In Design, Automation & Test in Europe Conference & Exhibition (DATE 2012) Proceedings (pp. 276–279). EDAA. http://hdl.handle.net/20.500.12708/54574
• Efficient Radiation-Hardening of a Muller C-Element / Veeravalli, V. S., & Steininger, A. (2012). Efficient Radiation-Hardening of a Muller C-Element. In 2012 Single Event Effects Symposium. 2012 Single Event Effects Symposium (SEE 2012), San Diego, USA, Non-EU. http://hdl.handle.net/20.500.12708/54573
• LFSR Implementation Using C-Elements / Veeravalli, V. S., & Steininger, A. (2012). LFSR Implementation Using C-Elements. In MEMICS 2012 (pp. 73–83). http://hdl.handle.net/20.500.12708/54572
• Radiation-Tolerant Combinational Gates - An Implementation Based Comparison / Veeravalli, V. S., & Steininger, A. (2012). Radiation-Tolerant Combinational Gates - An Implementation Based Comparison. In Design and Diagnostics of Electronic Circuits Systems (DDECS), 2012 IEEE 15th International Symposium on (pp. 115–120). http://hdl.handle.net/20.500.12708/54570
• Monitoring Single Event Transient Effects in Dynamic Mode / Veeravalli, V. S., & Steininger, A. (2012). Monitoring Single Event Transient Effects in Dynamic Mode. In 1st Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2012) (pp. 51–54). http://hdl.handle.net/20.500.12708/54568
• Parallel Runtime Verification of Temporal Properties for Embedded Software / Reinbacher, T., Geist, J., Moosbrugger, P., Horauer, M., & Steininger, A. (2012). Parallel Runtime Verification of Temporal Properties for Embedded Software. In Mechatronics and Embedded Systems and Applications (MESA), 2012 IEEE/ASME International Conference on (pp. 224–231). http://hdl.handle.net/20.500.12708/54567
  Project: CEVTES (2010–2013)
• A Runtime Verification Unit for Microcontrollers / Reinbacher, T., Horauer, M., & Steininger, A. (2012). A Runtime Verification Unit for Microcontrollers. In System, Software, SoC and Silicon Debug Conference (S4D), 2012 (pp. 1–6). http://hdl.handle.net/20.500.12708/54566
  Project: CEVTES (2010–2013)
• Supply Voltage Dependent On-chip Single Event Transient Pulse Shape Measurements in 90 nm Bulk CMOS under Alpha Irradiation / Hofbauer, M., Schweiger, K., Zimmermann, H., Giesen, U., Langner, F., Schmid, U., & Steininger, A. (2012). Supply Voltage Dependent On-chip Single Event Transient Pulse Shape Measurements in 90 nm Bulk CMOS under Alpha Irradiation. In Proceedings 21st European Conference on Radiation and its Effects on Components and Systems (RADECS’12). 21st European Conference on Radiation and its Effects on Components and Systems (RADECS’12), Biarritz, FRANCE, EU. http://hdl.handle.net/20.500.12708/54565
• Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip / Veeravalli, V. S., Steininger, A., Schmid, U., & Polzer, T. (2012). Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. In Proceedings 15th Euromicro Symposium on Digital System Design: Architectures, Methods and Tools (DSD’12) (pp. 8–17). http://hdl.handle.net/20.500.12708/54564
• Protecting Pipelined Asynchronous Communication Channels Against Single Event Upsets / Lechner, J., & Lampacher, M. (2012). Protecting Pipelined Asynchronous Communication Channels Against Single Event Upsets. In Computer Design (ICCD), 2012 IEEE 30th International Conference on (pp. 480–481). http://hdl.handle.net/20.500.12708/54527
• A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding / Lechner, J., Lampacher, M., & Polzer, T. (2012). A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding. In Application of Concurrency to System Design (ACSD), 2012 12th International Conference on (pp. 122–131). http://hdl.handle.net/20.500.12708/54526
• Designing Robust GALS Circuits with Triple Modular Redundancy / Lechner, J. (2012). Designing Robust GALS Circuits with Triple Modular Redundancy. In Dependable Computing Conference (EDCC), 2012 Ninth European (pp. 227–236). http://hdl.handle.net/20.500.12708/54525
• Protecting an Asynchronous NoC against Transient Channel Faults / Naqvi, S. R., Veeravalli, V. S., & Steininger, A. (2012). Protecting an Asynchronous NoC against Transient Channel Faults. In Proc. of 15th Euromicro Conference on Digital System Design (p. 8). http://hdl.handle.net/20.500.12708/54503
• An Asynchronous Router Architecture using Four-Phase Bundled Handshake Protocol / Naqvi, S. R. (2012). An Asynchronous Router Architecture using Four-Phase Bundled Handshake Protocol. In Proc. of The Seventh International Multi-Conference on Computing in the Global Information Technology (p. 6). http://hdl.handle.net/20.500.12708/54502
• Real-Time Runtime Verification on Chip / Reinbacher, T., Függer, M., & Brauer, J. (2012). Real-Time Runtime Verification on Chip. In Proc. of RV 2012: the 3rd International Conference on Runtime Verification. RV 2012: the 3rd International Conference on Runtime Verification, Istanbul, Non-EU. LNCS / Springer. http://hdl.handle.net/20.500.12708/54500
  Project: CEVTES (2010–2013)
• Brief Announcement: The Degrading Effect of Forgetting on a Synchronizer / Függer, M., Kößler, A., Nowak, T., & Zeiner, M. (2012). Brief Announcement: The Degrading Effect of Forgetting on a Synchronizer. In Stabilization, Safety, and Security of Distributed Systems (pp. 90–91). Lecture Notes in Computer Science. http://hdl.handle.net/20.500.12708/54498
• Efficient Checking of Link-Reversal-Based Concurrent Systems / Függer, M., & Widder, J. (2012). Efficient Checking of Link-Reversal-Based Concurrent Systems. In Lecture Notes in Computer Science (pp. 486–499). Lecture Notes in Computer Science. Springer Verlag. https://doi.org/10.1007/978-3-642-32940-1_34
• Messung der Auswirkungen von ionisierender Strahlung auf 90 nm CMOS Schaltungen / Hofbauer, M., Schweiger, K., Dietrich, H., Zimmermann, H., Schmid, U., & Giesen, U. (2012). Messung der Auswirkungen von ionisierender Strahlung auf 90 nm CMOS Schaltungen. http://hdl.handle.net/20.500.12708/37567

2011

• Replicated processors on a single die - How independently do they fail? / Steininger, A., & Tummeltshammer, P. (2011). Replicated processors on a single die - How independently do they fail? Elektrotechnik Und Informationstechnik : E & i, 128(6), 245–250. https://doi.org/10.1007/s00502-011-0005-9
• VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation / Fuchs, G., & Steininger, A. (2011). VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation. Journal of Electrical and Computer Engineering, 2011. https://doi.org/10.1155/2011/936712
  Project: DARTS (2005–2010)
• Hardware support for efficient testing of embedded software / Reinbacher, T., Steininger, A., Müller, T., Horauer, M., Brauer, J., & Kowalewski, S. (2011). Hardware support for efficient testing of embedded software. In International Conference on Mechatronic and Embedded Systems and Applications. The 7th ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications, Washington, Non-EU. ASME. http://hdl.handle.net/20.500.12708/54082
  Project: CEVTES (2010–2013)
• Past Time LTL Runtime Verification for Microcontroller Binary Code / Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., & Kowalewski, S. (2011). Past Time LTL Runtime Verification for Microcontroller Binary Code. In Formal Methods for Industrial Critical Systems (pp. 37–51). Springer Berlin / Heidelberg. https://doi.org/10.1007/978-3-642-24431-5_5
  Project: CEVTES (2010–2013)
• Automated test-trace inspection for microcontroller binary code / Reinbacher, T., Brauer, J., Schachinger, D., Steininger, A., & Kowalewski, S. (2011). Automated test-trace inspection for microcontroller binary code. In Runtime Verification (pp. 239–244). http://hdl.handle.net/20.500.12708/54078
  Project: CEVTES (2010–2013)
• Easy Impossibility Proofs for k-Set Agreement in Message Passing Systems / Biely, M., Robinson, P., & Schmid, U. (2011). Easy Impossibility Proofs for k-Set Agreement in Message Passing Systems. In OPODIS’11 (pp. 299–312). Springer Berlin / Heidelberg. http://hdl.handle.net/20.500.12708/54094
• Solving k-Set Agreement with Stable Skeleton Graphs / Biely, M., Robinson, P., & Schmid, U. (2011). Solving k-Set Agreement with Stable Skeleton Graphs. In 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum. International Parallel and Distributed Processing Symposium (IPDPS), Denver, Colorado, Austria. https://doi.org/10.1109/ipdps.2011.301
• The Asynchronous Bounded-Cycle Model / Robinson, P., & Schmid, U. (2011). The Asynchronous Bounded-Cycle Model. Theoretical Computer Science, 412(40), 5580–5601. https://doi.org/10.1016/j.tcs.2010.08.001
• Synchronous consensus under hybrid process and link failures / Biely, M., Schmid, U., & Weiss, B. (2011). Synchronous consensus under hybrid process and link failures. Theoretical Computer Science, 412(40), 5602–5630. https://doi.org/10.1016/j.tcs.2010.09.032
• On Self-Timed Circuits in Real-Time Systems / Ferringer, M. (2011). On Self-Timed Circuits in Real-Time Systems. International Journal of Reconfigurable Computing, 2011, 1–16. https://doi.org/10.1155/2011/972375
  Project: ARTS (2007–2011)
• On Efficient Checking of Link-reversal-based Concurrent Systems / Függer, M., & Widder, J. (2011). On Efficient Checking of Link-reversal-based Concurrent Systems. PUMA/RISE Seminar, Traunkirchen, Austria. http://hdl.handle.net/20.500.12708/85311
• Testing microcontroller software simulators / Reinbacher, T., Gückel, D., & Horauer, M. (2011). Testing microcontroller software simulators. In Workshop on Software Language Engineering for Cyber-physical Systems. WS4C 2011, Berlin, EU. http://hdl.handle.net/20.500.12708/54083
  Project: CEVTES (2010–2013)
• Brief Announcement: Easy Impossibility Proofs for k-Set Agreement in Message Passing Systems / Biely, M., Robinson, P., & Schmid, U. (2011). Brief Announcement: Easy Impossibility Proofs for k-Set Agreement in Message Passing Systems. In PODC’11 (pp. 227–228). ACM. http://hdl.handle.net/20.500.12708/54097
• Reconciling Fault-Tolerant Distributed Algorithms and Real-Time Computing / Moser, H., & Schmid, U. (2011). Reconciling Fault-Tolerant Distributed Algorithms and Real-Time Computing. In Structural Information and Communication Complexity (pp. 42–53). Springer Berlin / Heidelberg. https://doi.org/10.1007/978-3-642-22212-2_5
• Precise control flow reconstruction using boolean logic / Reinbacher, T., & Brauer, J. (2011). Precise control flow reconstruction using boolean logic. In Proceedings of the ninth ACM international conference on Embedded software - EMSOFT ’11. EMSOFT2011, ACM international conference on Embedded software, Taipei, Non-EU. ACM New York. https://doi.org/10.1145/2038642.2038662
  Project: CEVTES (2010–2013)
• Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation / Dolev, D., Függer, M., Lenzen, C., & Schmid, U. (2011). Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation. In Lecture Notes in Computer Science (pp. 163–177). Springer Berlin / Heidelberg. https://doi.org/10.1007/978-3-642-24550-3_14
• Partial is Full / Charron-Bost, B., Függer, M., Welch, J. L., & Widder, J. (2011). Partial is Full. In Structural Information and Communication Complexity (pp. 113–124). Springer Berlin / Heidelberg. https://doi.org/10.1007/978-3-642-22212-2_11
• Full Reversal Routing as a Linear Dynamical System / Charron-Bost, B., Függer, M., Welch, J. L., & Widder, J. (2011). Full Reversal Routing as a Linear Dynamical System. In Structural Information and Communication Complexity (pp. 101–112). Springer Berlin / Heidelberg. https://doi.org/10.1007/978-3-642-22212-2_10
• On the Performance of a Retransmission-Based Synchronizer / Nowak, T., Függer, M., & Kößler, A. (2011). On the Performance of a Retransmission-Based Synchronizer. In Structural Information and Communication Complexity (pp. 234–245). Springer Berlin / Heidelberg. http://hdl.handle.net/20.500.12708/54033
• Brief announcement / Charron-Bost, B., Fuegger, M., Welch, J. L., & Widder, J. (2011). Brief announcement. In Proceedings of the 23rd ACM symposium on Parallelism in algorithms and architectures - SPAA ’11. SPAA ’11, San Jose, California, USA, Non-EU. ACM. https://doi.org/10.1145/1989493.1989510
• Investigating the impact of process variations on an asynchronous Time-Triggered-Protocol controller / Ferringer, M. (2011). Investigating the impact of process variations on an asynchronous Time-Triggered-Protocol controller. In 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops (DSN-W). Dependable Systems and Networks Workshops (DSN-W), 2011 IEEE/IFIP 41st International Conference on, Hong-Kong, Non-EU. https://doi.org/10.1109/dsnw.2011.5958834
  Project: ARTS (2007–2011)
• Conversion and interfacing techniques for asynchronous circuits / Ferringer, M. (2011). Conversion and interfacing techniques for asynchronous circuits. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), Cottbus, Germany, EU. https://doi.org/10.1109/ddecs.2011.5783039
  Project: ARTS (2007–2011)
• Conversion of two- to four-phase delay-insensitive asynchronous circuits / Ferringer, M. (2011). Conversion of two- to four-phase delay-insensitive asynchronous circuits. In 2011 IEEE EUROCON - International Conference on Computer as a Tool. EUROCON 2011, Lisbon, EU. https://doi.org/10.1109/eurocon.2011.5929318
  Project: ARTS (2007–2011)

2010

• Test-Case Generation for Embedded Binary Code Using Abstract Interpretation / Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., & Kowalewski, S. (2010). Test-Case Generation for Embedded Binary Code Using Abstract Interpretation. In MEMICS proceedings (pp. 151–158). http://hdl.handle.net/20.500.12708/53554
  Project: CEVTES (2010–2013)
• A New Robust Interference Reduction Scheme for Low Complexity Direct-Sequence Spread-Spectrum Receivers: Optimization / Goiser, A. M. J., Khattab, S., Fassl, G., & Schmid, U. (2010). A New Robust Interference Reduction Scheme for Low Complexity Direct-Sequence Spread-Spectrum Receivers: Optimization. In 2010 Third International Conference on Communication Theory, Reliability, and Quality of Service. IEEE-Explore, Austria. IEEE Computer Society. https://doi.org/10.1109/ctrq.2010.51
• A New Robust Interference Reduction Scheme for Low Complexity Direct-Sequence Spread-Spectrum Receivers: Performance / Goiser, A., Khattab, S., Fassl, G., & Schmid, U. (2010). A New Robust Interference Reduction Scheme for Low Complexity Direct-Sequence Spread-Spectrum Receivers: Performance. In CTRQ-2010 (p. 7). IEEE Conference Proceedings. http://hdl.handle.net/20.500.12708/71631
• Topology Control for Fault-Tolerant Communication in Wireless Ad Hoc Networks / Thallner, B., Moser, H., & Schmid, U. (2010). Topology Control for Fault-Tolerant Communication in Wireless Ad Hoc Networks. Wireless Networks, 16(2), 387–404. https://doi.org/10.1007/s11276-008-0139-9
• In search of lost time / Charron-Bost, B., Hutle, M., & Widder, J. (2010). In search of lost time. Information Processing Letters, 110(21), 928–933. https://doi.org/10.1016/j.ipl.2010.07.017
• Challenges in Fault-Tolerant Distribiuted Real-Time Systems / Kößler, A. (2010). Challenges in Fault-Tolerant Distribiuted Real-Time Systems. RiSE Workshop TU Graz, Szentendre, Hungary, EU. http://hdl.handle.net/20.500.12708/85072
• Fault-Tolerant Distribiuted on-chip Algorithms / Függer, M. (2010). Fault-Tolerant Distribiuted on-chip Algorithms. PUMA 2010, Szentendre, Hungary, EU. http://hdl.handle.net/20.500.12708/85071
• Fault-Tolerant Distribiuted on-chip Algorithms / Függer, M. (2010). Fault-Tolerant Distribiuted on-chip Algorithms. FK 2010 (Forschungskooperation TU Wien - UNI Brno), Brno, Czech Republic, EU. http://hdl.handle.net/20.500.12708/85070
• Fault-Tolerant Distribiuted on-chip Algorithms / Függer, M. (2010). Fault-Tolerant Distribiuted on-chip Algorithms. RiSE GUGGING (IST AUSTRIA), Gugging (IST Austria), Austria. http://hdl.handle.net/20.500.12708/85069
• Synchrony and Time in Fault-Tolerant Distribiuted Algorithms / Schmid, U. (2010). Synchrony and Time in Fault-Tolerant Distribiuted Algorithms. In Formal Modeling and Analysis of Timed Systems. FORMATS 2010 (Formal Modeling and Analysis of Times Systems), Klosterneuburg, Austria, Austria. Springer. http://hdl.handle.net/20.500.12708/53556
• Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study. In 2010 NASA/ESA Conference on Adaptive Hardware and Systems. NASA/ESA 2010 (Conference on Adaptive Hardware and Systems), Anaheim, CA, USA, Non-EU. IEEE Computer Society. https://doi.org/10.1109/ahs.2010.5546277
• Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm. In 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W). WSDN 2010 (4th Workshop on Dependable and Secure Nanocomputing, Chicago, IL, USA, Non-EU. IEEE Computer Socitey. https://doi.org/10.1109/dsnw.2010.5542609
• A deterministic approach for hardware fault injection in asynchronous QDI logic / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). A deterministic approach for hardware fault injection in asynchronous QDI logic. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE. https://doi.org/10.1109/ddecs.2010.5491758
• Regional consecutive leader election in mobile ad-hoc networks / Chung, H. C., Robinson, P., & Welch, J. L. (2010). Regional consecutive leader election in mobile ad-hoc networks. In Proceedings of the 6th International Workshop on Foundations of Mobile Computing - DIALM-POMC ’10. ACM SIGACT/SIGMOBILE (International Workshop on FOUNDATIONS OF MOBILE COUMPUTING), Cambridge, Massachusetts, USA, Non-EU. ACM. https://doi.org/10.1145/1860684.1860701
• Brief Announcement: Regional Consecutive Leader Election in Mobile Ad-Hoc Networks / Chung, H. C., Robinson, P., & Welch, J. L. (2010). Brief Announcement: Regional Consecutive Leader Election in Mobile Ad-Hoc Networks. In Algorithms for Sensor Systems (pp. 89–91). Springer. https://doi.org/10.1007/978-3-642-16988-5_8
• Real-Time Analysis of Round-based Distributed Algorithms / Kößler, A., Moser, H., & Schmid, U. (2010). Real-Time Analysis of Round-based Distributed Algorithms. In Proceedings of the 1st International Real-Time Scheduling Open Problems Seminar (pp. 9–11). http://hdl.handle.net/20.500.12708/53495
• Investigating Self-Timed Circuits for the Time-Triggered Protocol / Ferringer, M. (2010). Investigating Self-Timed Circuits for the Time-Triggered Protocol. In Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 (pp. 101–108). KIT Scientific Publishing - DFG. http://hdl.handle.net/20.500.12708/53494
  Project: ARTS (2007–2011)
• Towards self-timed logic in the Time-Triggered Protocol / Ferringer, M. (2010). Towards self-timed logic in the Time-Triggered Protocol. In 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W). DSN 2010 (International Conference on Dependable Systems and Networks), Chicago, IL, USA, Non-EU. IEEE Computer Society. https://doi.org/10.1109/dsnw.2010.5542607
  Project: THETA (2004–2008)
• How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining / Függer, M., Dielacher, A., & Schmid, U. (2010). How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining. In 2010 European Dependable Computing Conference. EDCC - 8 (European Dependable Computing Conference), Valencia, Spain, EU. IEEE Computer Society. https://doi.org/10.1109/edcc.2010.35
• Enhancing pipelined processor architectures with fast autonomous recovery of transient faults / Jeitler, M., Lechner, J., & Steininger, A. (2010). Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE Computer Society. https://doi.org/10.1109/ddecs.2010.5491776
• Low Latency Recovery from Transient Faults for Pipelined Processor Architectures / Jeitler, M., & Lechner, J. (2010). Low Latency Recovery from Transient Faults for Pipelined Processor Architectures. In 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. DSD 2010 (Euromicro Conference on Digital System Design), Lille, France, EU. IEEE Computer Society. https://doi.org/10.1109/dsd.2010.87

2009

• Brief Announcment: Weak Synchrony Models and Failure Detectors for Message Passing (𝑘-)Set Agreement / Biely, M., Robinson, P., & Schmid, U. (2009). Brief Announcment: Weak Synchrony Models and Failure Detectors for Message Passing (𝑘-)Set Agreement. In I. Keidar (Ed.), Distributed Computing: 23rd International Symposium, DISC 2009, Elche, Spain, September 23-25, 2009, Proceedings (pp. 360–361). Springer. https://doi.org/10.1007/978-3-642-04355-0_38
• Chasing the Weakest System Model for Implementing Ω and Consensus / Hutle, M., Malkhi, D., Schmid, U., & Zhou, L. (2009). Chasing the Weakest System Model for Implementing Ω and Consensus. IEEE Transactions on Dependable and Secure Computing, 6(4), 269–281. https://doi.org/10.1109/tdsc.2008.24
• Is Asynchronous Logic More Robust Than Synchronous Logic? / Rahbaran, B., & Steininger, A. (2009). Is Asynchronous Logic More Robust Than Synchronous Logic? IEEE Transactions on Dependable and Secure Computing, 6(4), 282–294. https://doi.org/10.1109/tdsc.2008.37
• Impossibility Results and Lower Bounds For Consensus Under Link Failures / Schmid, U., Weiss, B., & Keidar, I. (2009). Impossibility Results and Lower Bounds For Consensus Under Link Failures. SIAM Journal on Computing, 38(5), 1912–1951. https://doi.org/10.1137/s009753970443999x
• Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - A Combined Formal and Experimental Approach / Függer, M., Steininger, A., & Armengaud, E. (2009). Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - A Combined Formal and Experimental Approach. IEEE Transactions on Industrial Informatics, 5(2), 132–145. http://hdl.handle.net/20.500.12708/166191
  Project: EXTRACT (2005–2008)
• Optimal Message-Driven Implementations of Omega with Mute Processes / Widder, J., & Biely, M. (2009). Optimal Message-Driven Implementations of Omega with Mute Processes. ACM Transactions on Autonomous and Adaptive Systems, 4(1). https://doi.org/10.1145/1462187
• The Theta-Model: achieving synchrony without clocks / Widder, J., & Schmid, U. (2009). The Theta-Model: achieving synchrony without clocks. Distributed Computing, 22(1), 29–47. https://doi.org/10.1007/s00446-009-0080-x
• Weak Synchrony Models and Failure Detectors for Message Passing (𝑘-)Set Agreement / Biely, M., Robinson, P., & Schmid, U. (2009). Weak Synchrony Models and Failure Detectors for Message Passing (𝑘-)Set Agreement. In T. Abdelzaher, M. Raynal, & N. Santoro (Eds.), Principles of Distributed Systems: 13th International Conference, OPODIS 2009, Nîmes, France, December 15-18, 2009. Proceedings (pp. 285–299). Springer. https://doi.org/10.1007/978-3-642-10877-8_23
• A Metastability-Free Multi-synchronous Communication Scheme for SoCs / Polzer, T., Handl, T., & Steininger, A. (2009). A Metastability-Free Multi-synchronous Communication Scheme for SoCs. In R. Guerraoui & F. Petit (Eds.), Stabilization, Safety, and Security of Distributed Systems: 11th International Symposium, SSS 2009, Lyon, France, November 3-6, 2009. Proceedings (pp. 578–592). Springer. https://doi.org/10.1007/978-3-642-05118-0_40
  Project: DARTS (2005–2010)
• Consensus When All Processes May Be Byzantine for Some Time / Biely, M., & Hutle, M. (2009). Consensus When All Processes May Be Byzantine for Some Time. In Lecture Notes in Computer Science (pp. 120–132). Lecture Notes in Conputer Science / Springer Verlag. https://doi.org/10.1007/978-3-642-05118-0_9
• Implications of VLSI Fault Models and Distributed Systems Failure Models --- A Hardware Designer's View / Fuchs, G. (2009). Implications of VLSI Fault Models and Distributed Systems Failure Models --- A Hardware Designer’s View. In Fault-Tolerant Distributed Algorithms on VLSI Chips (p. ?). Leibniz Zentrum Informatik. http://hdl.handle.net/20.500.12708/52888
  Project: DARTS (2005–2010)
• Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation / Jeitler, M., & Lech, J. (2009). Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation. In 2009 International Conference on Reconfigurable Computing and FPGAs. ReConFig 2009 (International Conference on ReConFigurable Computing and FPGAs), Cancun, Quintana Roo, Mexico, Non-EU. CPS. https://doi.org/10.1109/reconfig.2009.35
• Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection / Jeitler, M., & Lechner, J. (2009). Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection. In MEMICS 2009 proceedings (pp. 110–117). Universität Brno. http://hdl.handle.net/20.500.12708/52876
• FuSE - a hardware accelerated HDL fault injection tool / Jeitler, M., Delvai, M., & Reichör, S. (2009). FuSE - a hardware accelerated HDL fault injection tool. In 2009 5th Southern Conference on Programmable Logic (SPL). SPL 2009 (Southern Conference on Programmable Logic), Sao Carlos, Brazil, Non-EU. IEEE. https://doi.org/10.1109/spl.2009.4914906
• Fault Tolerant Distribiuted Algorithms and VLSI - An Appetizer / Charron-Bost, B., Dolev, S., Ebergen, J., & Schmid, U. (2009). Fault Tolerant Distribiuted Algorithms and VLSI - An Appetizer. In Fault-Tolerant Distributed Algorithms on VLSI Chips (p. ?). Leibniz Zentrum Informatik. http://hdl.handle.net/20.500.12708/52874
• Error Containment in the Presence of Metastability / Steininger, A. (2009). Error Containment in the Presence of Metastability. In Fault-Tolerant Distributed Algorithms on VLSI Chips (p. ?). Leibniz Zentrum Informatik. http://hdl.handle.net/20.500.12708/52873
• Remote Measurement of Local Oscillator Drifts in FlexRay Networks / Armengaud, E., & Steininger, A. (2009). Remote Measurement of Local Oscillator Drifts in FlexRay Networks. In DATE09 (pp. 1082–1087). Springer. http://hdl.handle.net/20.500.12708/52872
  Project: EXTRACT (2005–2008)
• On the Risk of Fault Coupling over the Chip Substrate / Tummeltshammer, P., & Steininger, A. (2009). On the Risk of Fault Coupling over the Chip Substrate. In 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece, EU. IEEE Computer Society. https://doi.org/10.1109/dsd.2009.185
• Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic / Friesenbichler, W., & Steininger, A. (2009). Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic. In 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece, EU. IEEE Computer Society. https://doi.org/10.1109/dsd.2009.142
• On the Stability and Robustness of Non-Synchronous Circuits with Timing Loops / Függer, M., Fuchs, G., & Steininger, A. (2009). On the Stability and Robustness of Non-Synchronous Circuits with Timing Loops. In WSDN 2009 (pp. 45–50). Springer. http://hdl.handle.net/20.500.12708/52868
  Project: DARTS (2005–2010)
• How to Speed-up Fault-tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining / Dielacher, A., & Függer, M. (2009). How to Speed-up Fault-tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining. In PODC’09 (pp. 276–277). ACM. http://hdl.handle.net/20.500.12708/52866
• On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme / Fuchs, G., Függer, M., & Steininger, A. (2009). On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme. In 2009 15th IEEE Symposium on Asynchronous Circuits and Systems. ASYNC 2009 (International Symposium on Asynchronous Circuits and Systems), Chapel Hill, North Carolina, Non-EU. IEEE Computer Society. https://doi.org/10.1109/async.2009.15
  Project: DARTS (2005–2010)
• Power Supply Induced Common Cause Faults - Experimental Assessment of Potential Countermeasures / Tummeltshammer, P., & Steininger, A. (2009). Power Supply Induced Common Cause Faults - Experimental Assessment of Potential Countermeasures. In DSN 2009 - Full Program (pp. 449–457). Springer. http://hdl.handle.net/20.500.12708/52864
• Coupling Asynchronous Signals into Asynchronous Logic / Ferringer, M. (2009). Coupling Asynchronous Signals into Asynchronous Logic. In Austrochip (pp. 97–102). Institut für Elektronik - TU Graz. http://hdl.handle.net/20.500.12708/52854
  Project: ARTS (2007–2011)
• Link Reversal: How to Play Better to Work Less / Charron-Bost, B., Welch, J. L., & Widder, J. (2009). Link Reversal: How to Play Better to Work Less. In Algorithmic Aspects of Wireless Sensor Networks (pp. 88–101). Springer. https://doi.org/10.1007/978-3-642-05434-1_10
• Routing without ordering / Charron-Bost, B., Gaillard, A., Welch, J., & Widder, J. (2009). Routing without ordering. In Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures - SPAA ’09. SPAA 2009 (Parallelism in Algorithms and Architectures), Calgary, Alberta, Canada, Non-EU. ACM. https://doi.org/10.1145/1583991.1584034
• On the role of the power supply as an entry for common cause faults—An experimental analysis / Tummeltshammer, P., & Steininger, A. (2009). On the role of the power supply as an entry for common cause faults—An experimental analysis. In 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. DDECS 2009 (Design and Diagnostics of Electronic Circuits and Systems), Liberec, Czech Republic, EU. IEEE. https://doi.org/10.1109/ddecs.2009.5012118
• ARROW - A Generic Hardware Fault Injection Tool for NoCs / Birner, M., & Handl, T. (2009). ARROW - A Generic Hardware Fault Injection Tool for NoCs. In 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece, EU. IEEE Computer Society. https://doi.org/10.1109/dsd.2009.223

2008

• Towards a Systematic Test for Embedded Automotive Communication Systems / Armengaud, E., Steininger, A., & Horauer, M. (2008). Towards a Systematic Test for Embedded Automotive Communication Systems. IEEE Transactions on Industrial Informatics, 4(3), 146–155. https://doi.org/10.1109/TII.2008.2002704
  Project: STEACS (2003–2008)
• Exploring Hardware Software Partitioning on the Example of a Fingerprint Verification System / Hepp, S., Klima, G., Kadlec, A., Krammer, L., Luckner, W., Prokesch, D., Resch, S., Wasicek, A., Wilhelm, J., Tummeltshammer, P., & Delvai, M. (2008). Exploring Hardware Software Partitioning on the Example of a Fingerprint Verification System. In Proc. of the 16th Austrian Workshop on Microelectronics 2008 (pp. 7–12). http://hdl.handle.net/20.500.12708/52482
• Automated Generation of Explicit Connectors for Component Based Hardware/Software Interaction in Embedded Real-Time Systems / Forster, W., Kutschera, C., Steininger, A., & Göschka, K. M. (2008). Automated Generation of Explicit Connectors for Component Based Hardware/Software Interaction in Embedded Real-Time Systems. In Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS 2008), (IPDPS 2008) (pp. 1–8). IEEE Computer Society. http://hdl.handle.net/20.500.12708/52268
• Statechart Modelling for ARGESIM Benchmark C10 'Dining Philosophers Problem II' using Simulink/Stateflow / Legourski, V., Huang, Y., Cevan, O., & Breitenecker, F. (2008). Statechart Modelling for ARGESIM Benchmark C10 “Dining Philosophers Problem II” using Simulink/Stateflow. Simulation News Europe SNE, 18(1), 39–40. http://hdl.handle.net/20.500.12708/171151
• An Object-oriented DEV Approach to ARGESIM Benchmark C16 'Restaurant Business Dynamics' using Enterprise Dynamics / Tauböck, S. M., Jahn, P., Polzer, T., & Schuster, A. (2008). An Object-oriented DEV Approach to ARGESIM Benchmark C16 “Restaurant Business Dynamics” using Enterprise Dynamics. Simulation News Europe SNE, 18(1), 41–42. http://hdl.handle.net/20.500.12708/171152
• An Object-oriented Solution to ARGESIM Benchmark C4 'Dining Philosophers Problem' implemented with AnyLogic / Gyimesi, M., Dielacher, A., Handl, T., & Wittmann, C. (2008). An Object-oriented Solution to ARGESIM Benchmark C4 “Dining Philosophers Problem” implemented with AnyLogic. Simulation News Europe SNE, 18(1), 31–32. http://hdl.handle.net/20.500.12708/171148
• Towards a real-time distribiuted computing model / Moser, H. (2008). Towards a real-time distribiuted computing model. Theoretical Computer Science, 410(6–7), 629–659. https://doi.org/10.1016/j.tcs.2008.10.012
• The Asynchronous Bounded Cycle Model / Robinson, P., & Schmid, U. (2008). The Asynchronous Bounded Cycle Model. In Lecture Notes in Computer Science. 10 International Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS 2008), Detroit, USA, Non-EU. Lecture Notes in Conputer Science / Springer Verlag. https://doi.org/10.1007/978-3-540-89335-6
• An Operating System for a Time-Predictable Computing Node / Khyo, G., Puschner, P., & Delvai, M. (2008). An Operating System for a Time-Predictable Computing Node. In Software Technologies for Embedded and Ubiquitous Systems (pp. 150–161). Lecture Notes in Computer Science / Springer Verlag. https://doi.org/10.1007/978-3-540-87785-1_14
• Fault Tolerant Four-State Logic by Using Self-Healing Cells / Panhofer, T., Friesenbichler, W., & Delvai, M. (2008). Fault Tolerant Four-State Logic by Using Self-Healing Cells. In 2008 IEEE International Conference on Computer Design (p. 6). IEEE. http://hdl.handle.net/20.500.12708/52475
• Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits / Friesenbichler, W., Panhofer, T., & Delvai, M. (2008). Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits. In 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008, Bratislava, Slovakia, EU. IEEE. https://doi.org/10.1109/ddecs.2008.4538799
• A Concept for Hybrid Fault Injection in Distributed Systems / Trödhandl, C., & Weiss, B. (2008). A Concept for Hybrid Fault Injection in Distributed Systems. In Testing: Academic and Industrial Conference --- Practice and Research Techniques (Fast Abstracts). Testing: Academic and Industrial Conference --- Practice and Research Techniques, Windsor, United Kingdom, EU. http://hdl.handle.net/20.500.12708/52265
• Experimental Evaluation of the FlexRay Clock Synchronization Service / Armengaud, E. (2008). Experimental Evaluation of the FlexRay Clock Synchronization Service. In 20. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (pp. 85–89). http://hdl.handle.net/20.500.12708/52483
  Project: EXTRACT (2005–2008)
• Optimal Deterministic Remote Clock Estimation in Real-Time Systems / Moser, H., & Schmid, U. (2008). Optimal Deterministic Remote Clock Estimation in Real-Time Systems. In Lecture Notes in Computer Science (pp. 363–387). Lecture Notes in Computer Science / Springer Verlag. https://doi.org/10.1007/978-3-540-92221-6_24
• Implementation of a Design Tool for Automated Generation of Four State Logic Circuits / Lechner, J., & Delvai, M. (2008). Implementation of a Design Tool for Automated Generation of Four State Logic Circuits. In Proceedings of the Junior Scientist Conference 2008 (pp. 85–86). http://hdl.handle.net/20.500.12708/52477
• Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras / Ambrosch, K., Humenberger, M., Kubinger, W., & Steininger, A. (2008). Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras. In 2008 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops. IEEE Conference on Computer Vision and Pattern Recognition, 2008. CVPR ’08, Anchorage, Alaska, USA, Non-EU. https://doi.org/10.1109/cvprw.2008.4563146
• Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks / Milbredt, P., Steininger, A., & Horauer, M. (2008). Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks. In 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008). IEEE International Workshop on Electronic Design, Test and Applications, Hong-Kong, Non-EU. https://doi.org/10.1109/delta.2008.74
• Safe deterministic replay for stimulating the clock synchronization algorithm in time-triggered systems / Armengaud, E., Függer, M., & Steininger, A. (2008). Safe deterministic replay for stimulating the clock synchronization algorithm in time-triggered systems. In 2008 IEEE International Workshop on Factory Communication Systems. WFCS, Torino, Italy, EU. https://doi.org/10.1109/wfcs.2008.4638707
  Project: EXTRACT (2005–2008)
• An investigation of the clique problem in FlexRay / Milbredt, P., Horauer, M., & Steininger, A. (2008). An investigation of the clique problem in FlexRay. In 2008 International Symposium on Industrial Embedded Systems. SIES´2008 Third international symposium on industrial embedded systems, Montpellier - La Grande Motte, France, EU. https://doi.org/10.1109/sies.2008.4577700
• Exploring the Usefulness of the Gate-level Stuck-at Fault Model for Muller C-Elements / Grahsl, J., Handl, T., & Steininger, A. (2008). Exploring the Usefulness of the Gate-level Stuck-at Fault Model for Muller C-Elements. In 20. Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen (pp. 165–169). http://hdl.handle.net/20.500.12708/52459
  Project: DARTS (2005–2010)
• Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip / Fuchs, G., Függer, M., Schmid, U., & Steininger, A. (2008). Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip. In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. 11th EUROMICRO Conference on Digital System Design (DSD 2008), Parma, Italien, EU. IEEE. https://doi.org/10.1109/dsd.2008.65
  Project: DARTS (2005–2010)
• Keynote: Distributed Algorithms and VLSI / Schmid, U. (2008). Keynote: Distributed Algorithms and VLSI. In Lecture Notes in Computer Science (pp. 3–3). Lecture Notes in Conputer Science / Springer Verlag. https://doi.org/10.1007/978-3-540-89335-6_3
• The asynchronous bounded-cycle model / Schmid, U., & Robinson, P. (2008). The asynchronous bounded-cycle model. In Proceedings of the twenty-seventh ACM symposium on Principles of distributed computing - PODC ’08. ACM Symposium on Principles of Distributed Computing, Las Vegas, Nevada, Austria. Association for Computing Machinery (ACM). https://doi.org/10.1145/1400751.1400815

2007

• FIT-IT Projekt DARTS: Dezentrale fehlertolerante Taktgenerierung / Schmid, U., Steininger, A., & Sust, M. (2007). FIT-IT Projekt DARTS: Dezentrale fehlertolerante Taktgenerierung. Elektrotechnik und Informationstechnik : e & i, 124(1–2), 3–8. https://doi.org/10.1007/s00502-006-0409-0
• LTCC: a fascinating technology platform for miniaturized devices / Schmid, U. (2007). LTCC: a fascinating technology platform for miniaturized devices. In T. Becker, C. Cané, & N. S. Barker (Eds.), Smart Sensors, Actuators, and MEMS III (Proceedings Volume). SPIE. https://doi.org/10.1117/12.722793
• Graphical Microcontroller Programming (GMCP) / Jahn, P., & Polzer, T. (2007). Graphical Microcontroller Programming (GMCP). IEEE International Conference on Industrial Informatics - INDIN 2007, Wien, Austria. http://hdl.handle.net/20.500.12708/84609
• Towards a Systematic Design of Fault-Tolerant Asynchronous Circuits / Schmid, U., Steininger, A., & Veith, H. (2007). Towards a Systematic Design of Fault-Tolerant Asynchronous Circuits. In Fachtagung Zuverlässigkeit und Entwurf (pp. 173–174). VDE Verlag. http://hdl.handle.net/20.500.12708/51805
• A Perspective of Fault-Tolerant Clock Synchronization / Schmid, U. (2007). A Perspective of Fault-Tolerant Clock Synchronization. In IEEE Symposium on Precision Clock Synchronization for Measurement, Control and Communication. 2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication, Vienna, Austria. http://hdl.handle.net/20.500.12708/52101
• Clock Synchronization in the Byzantine-Recovery Failure Model / Anceaume, E., Delporte-Gallet, C., Fauconnier, H., Hurfin, M., & Widder, J. (2007). Clock Synchronization in the Byzantine-Recovery Failure Model. In International Conference On Principles Of DIstributed System (pp. 90–104). http://hdl.handle.net/20.500.12708/52073
• Hardware Implementation of an SAD based stereo vision algorithm / Ambrosch, K., Humenberger, M., Kubinger, W., & Steininger, A. (2007). Hardware Implementation of an SAD based stereo vision algorithm. In Proceedings of Third IEEE Workshop on Embedded Computer Vision. Third IEEE Workshop on Embedded Computer Vision, Minneapolis, Non-EU. http://hdl.handle.net/20.500.12708/52065
• Concepts and Tools for the Test of the Communication Sub-System of Time-Triggered Distributed Embedded Systems / Horauer, M., Armengaud, E., & Steininger, A. (2007). Concepts and Tools for the Test of the Communication Sub-System of Time-Triggered Distributed Embedded Systems. In ASME 2007 International Conference on Design Engineering Technical Conferences & Computers and Information in Engineering. International Conference on Design Engineering Technical Conferences & Computers and Information in Engineering (ASME), Las Vegas, Non-EU. http://hdl.handle.net/20.500.12708/52064
  Project: STEACS (2003–2008)
• A Fail-Silent Reconfigurable Superscalar Processor / Kottke, T., & Steininger, A. (2007). A Fail-Silent Reconfigurable Superscalar Processor. In 13th Pacific Rim International Symposium on Dependable Computing (PRDC’07), Melbourne (pp. 232–239). http://hdl.handle.net/20.500.12708/52063
• Exploring Hardware Software Partitioning on the Example of a Face Recognition System / Angerer, C., Cevan, O., Fauster, L., Huang, Y., Huber, B., Legourski, V., Pirker, S., Polzer, T., Reichhard, D., Rigler, D., Schuster, A., Weirich, B., Tummeltshammer, P., & Delvai, M. (2007). Exploring Hardware Software Partitioning on the Example of a Face Recognition System. In Austrochip - Workshop on Microelectronics (pp. 121–127). http://hdl.handle.net/20.500.12708/52062
• The Effect of Quartz Drift on Convergence-Average based Clock Synchronization / Armengaud, E., Steininger, A., & Hanzlik, A. (2007). The Effect of Quartz Drift on Convergence-Average based Clock Synchronization. In Proceedings of the 12th IEEE Conference on Emerging Technologies and Factory Automation (pp. 1123–1130). http://hdl.handle.net/20.500.12708/52061
  Project: EXTRACT (2005–2008)
• A Novel Interconnection Approach for Globally Asynchronous Locally Synchronous Circuits / Armengaud, E., & Forster, W. (2007). A Novel Interconnection Approach for Globally Asynchronous Locally Synchronous Circuits. In Austrochip - Workshop on Microelectronics (pp. 107–113). http://hdl.handle.net/20.500.12708/52060
• Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit / Handl, T., Steininger, A., & Kempf, G. (2007). Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit. In Proceedings IDT’07 - The Second International Design and Test Workshop (pp. 115–119). http://hdl.handle.net/20.500.12708/52055
  Project: DARTS (2005–2010)
• SELF-HEALING CIRCUITS FOR SPACE-APPLICATIONS / Delvai, M., & Panhofer, T. (2007). SELF-HEALING CIRCUITS FOR SPACE-APPLICATIONS. In Proceedings of 17th INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (pp. 505–506). http://hdl.handle.net/20.500.12708/52054
• SAFE - A Scalable Environment for Automated Transistor Level Fault Effect Analysis / Grahsl, J., Handl, T., Steininger, A., & Kempf, G. (2007). SAFE - A Scalable Environment for Automated Transistor Level Fault Effect Analysis. In Austrochip - Workshop on Microelectronics (pp. 91–98). http://hdl.handle.net/20.500.12708/52053
  Project: DARTS (2005–2010)
• Synchronous Consensus with Mortal Byzantines / Widder, J., Gridling, G., Weiss, B., & Blanquart, J.-P. (2007). Synchronous Consensus with Mortal Byzantines. In Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks. IEEE Conference on Dependable Systems and Networks (DSN), Philadelphia, PA, USA, Non-EU. http://hdl.handle.net/20.500.12708/52033
• Relating Stabilizing Timing Assumptions to Stabilizing Failure Detectors Regarding Solvability and Efficiency / Biely, M., Hutle, M., Penso, L. D., & Widder, J. (2007). Relating Stabilizing Timing Assumptions to Stabilizing Failure Detectors Regarding Solvability and Efficiency. In stabilization. Ninth International Symposium on Stabilization, Safety, and Security of Distributed Systems (SSS 2007), Paris, EU. http://hdl.handle.net/20.500.12708/52032
• Tolerating Corrupted Communication / Biely, M., Charron-Bost, B., Gaillard, A., Hutle, M., Schiper, A., & Widder, J. (2007). Tolerating Corrupted Communication. In 26th ACM Symposium on Principles of Distributed Computing (PODC’07) (pp. 244–253). http://hdl.handle.net/20.500.12708/52017
• Vergleich zweier zwischen Sicherheit und Performanz rekonfigurierbarer Prozessorsysteme / Kottke, T., & Steininger, A. (2007). Vergleich zweier zwischen Sicherheit und Performanz rekonfigurierbarer Prozessorsysteme. In 19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen. 19. ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Errlangen, EU. http://hdl.handle.net/20.500.12708/51797
• An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip / Handl, T., Steininger, A., & Kempf, G. (2007). An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip. In 19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (pp. 66–70). http://hdl.handle.net/20.500.12708/51796
  Project: DARTS (2005–2010)
• Booting Clock Synchronization in Partially Synchronous Systems with Hybrid Process and Link Failures / Widder, J., & Schmid, U. (2007). Booting Clock Synchronization in Partially Synchronous Systems with Hybrid Process and Link Failures. In Distributed Computing (pp. 115–140). Springer-Verlag. http://hdl.handle.net/20.500.12708/25412
• Time-Multiplexed Multiple Constant Multiplication / Tummeltshammer, P., Hoe, James. C., & Pueschel, M. (2007). Time-Multiplexed Multiple Constant Multiplication. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (pp. 1551–1563). IEEE. http://hdl.handle.net/20.500.12708/25411

2006

• The DARTS project / Steininger, A. (2006). The DARTS project. ESA Workshop, Aarhus, Denmark, EU. http://hdl.handle.net/20.500.12708/84591
• The ECS group's hardware related research activities / Steininger, A. (2006). The ECS group’s hardware related research activities. Firma Freescale, München, EU. http://hdl.handle.net/20.500.12708/84590
• Synchronous Consensus with Mortal Byzantines / Widder, J., Gridling, G., Weiss, B., & Blanquart, J.-P. (2006). Synchronous Consensus with Mortal Byzantines. Dagstuhl Seminar 06371. From Security to Dependability, Dagstuhl, EU. http://hdl.handle.net/20.500.12708/84588
• Wissenschaftliche Forschung - Quo vadis? / Schmid, U. (2006). Wissenschaftliche Forschung - Quo vadis? IKT in Österreich 2006, Wien, Austria. http://hdl.handle.net/20.500.12708/84587
• Reconciling Distributed Computing Models and Real-Time Systems / Moser, H., & Thallner, B. (2006). Reconciling Distributed Computing Models and Real-Time Systems. In Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS’06) (pp. 73–76). http://hdl.handle.net/20.500.12708/51664
• Construction of a Fault-Tolerant Wireless Communication Topology Using Distributed Agreement / Moser, H., & Thallner, B. (2006). Construction of a Fault-Tolerant Wireless Communication Topology Using Distributed Agreement. In DIWANS ’06: Proceedings of the 2006 workshop on Dependability issues in wireless ad hoc networks and sensor networks (pp. 35–43). http://hdl.handle.net/20.500.12708/51663
• Construction of a Fault-Tolerant Wireless Communication Topology Using Distributed Agreement / Moser, H., & Schmid, U. (2006). Construction of a Fault-Tolerant Wireless Communication Topology Using Distributed Agreement. In Junior Scientiest Conferenve 2006 (pp. 47–48). http://hdl.handle.net/20.500.12708/51662
• Optimal clock synchronization revisited: Upper and lower bounds in real-time systems / Moser, H., & Schmid, U. (2006). Optimal clock synchronization revisited: Upper and lower bounds in real-time systems. In Principles of Distributed Systems (pp. 94–109). http://hdl.handle.net/20.500.12708/51661
• Environments for Remote Teaching in Embedded Systems Courses / Trödhandl, C., Weiss, B., Handl, T., & Proske, M. (2006). Environments for Remote Teaching in Embedded Systems Courses. In 2006 ERCIM / DECOS Workshop on Dependable Embedded Systems. ERCIM / DECOS Workshop on Dependable Embedded Systems, Cavtat, Non-EU. http://hdl.handle.net/20.500.12708/51656
  Project: SCDL (2004–2007)
• Brief Announcement: Chasing the Weakest System Model for Implementing Omega and Consensus / Hutle, M., Malkhi, D., Schmid, U., & Zhou, L. (2006). Brief Announcement: Chasing the Weakest System Model for Implementing Omega and Consensus. In Stabilization, Safety, and Security of Distributed Systems. 8th International Symposium on Stabilization, Safety, and Security of Distributed Systems, Dallas, Non-EU. http://hdl.handle.net/20.500.12708/51635
• Distance Labs - Embedded Systems @home / Proske, M., Trödhandl, C., & Handl, T. (2006). Distance Labs - Embedded Systems @home. In Journal of Computational Information Systems (pp. 435–444). http://hdl.handle.net/20.500.12708/51634
  Project: SCDL (2004–2007)
• Anytime, Everywhere - Approaches to Distance Labs in Embedded Systems Education - Extended Abstract / Proske, M., & Trödhandl, C. (2006). Anytime, Everywhere - Approaches to Distance Labs in Embedded Systems Education - Extended Abstract. In Proceedings of ICTTA 2006 (pp. 205–206). IEEE. http://hdl.handle.net/20.500.12708/51633
• Recovery Mechanisms for Dual Core Architectures / El Salloum, C., Steininger, A., & Tummeltshammer, P. (2006). Recovery Mechanisms for Dual Core Architectures. In 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, Proceedings (pp. 380–388). http://hdl.handle.net/20.500.12708/51601
• Simulating Distributed Real-Time Systems / Albeseder, D., & Widder, J. (2006). Simulating Distributed Real-Time Systems. In Junior Scientist Conference 2006 (pp. 83–84). http://hdl.handle.net/20.500.12708/51573
• Implementation of an FPGA-Based Hardware Fault Injector / Handl, T., & Steininger, A. (2006). Implementation of an FPGA-Based Hardware Fault Injector. In Junior Scientist Conference 2006 (pp. 23–24). http://hdl.handle.net/20.500.12708/51572
• Efficient Position-based Communication in Wireless Ad-hoc Networks / Stratil, H., & Schmid, U. (2006). Efficient Position-based Communication in Wireless Ad-hoc Networks. In Junior Scientist Conference 2006 (pp. 75–76). http://hdl.handle.net/20.500.12708/51571
• Time-Multiplexed Multiple Constant Multiplication / Tummeltshammer, P., & Steininger, A. (2006). Time-Multiplexed Multiple Constant Multiplication. In Junior Scientist Conference 2006 (pp. 77–78). http://hdl.handle.net/20.500.12708/51570
• A Practical Comparison of Logic Design Styles / Delvai, M., & Steininger, A. (2006). A Practical Comparison of Logic Design Styles. In The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 3 (pp. 61–66). http://hdl.handle.net/20.500.12708/51530
• Asynchronous Logic Design - from Concepts to Implementation / Delvai, M., & Steininger, A. (2006). Asynchronous Logic Design - from Concepts to Implementation. In The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 1 (pp. 81–86). http://hdl.handle.net/20.500.12708/51528
• Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods / Delvai, M., & Steininger, A. (2006). Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods. In 9th Euromicro Conference on Digital System Design - Architectures, Methods and Tools (pp. 131–136). http://hdl.handle.net/20.500.12708/51526
• Design Variety in Hardware/Software Codesign - Implementations of an AES Encoder / Ambrosch, K., Helpa, C., Lechner, J., Leidenfrost, R., Panhofer, T., platschek, A., Ramberger, S., Stadler, U., Steiner, D., Trinkl, H., Widtmann, C., & Delvai, M. (2006). Design Variety in Hardware/Software Codesign - Implementations of an AES Encoder. In Austrochip Mikroelektroniktagung (pp. 181–188). Austrochip 2006. http://hdl.handle.net/20.500.12708/51525
• A µController Lab for Distance Learning / Gridling, G., & Weiss, B. (2006). A µController Lab for Distance Learning. In EWME 2006 - Proceedings (pp. 129–132). http://hdl.handle.net/20.500.12708/51522
• Optimal Message-Driven Implementations of Omega with Mute Processes / Biely, M., & Widder, J. (2006). Optimal Message-Driven Implementations of Omega with Mute Processes. In Stabilization, Safety, and Security of Distributed Systems (pp. 110–121). http://hdl.handle.net/20.500.12708/51523
• Remote Target Monitoring in Embedded Systems Lab Courses using a Sensor Network / Trödhandl, C., Proske, M., & Elmenreich, W. (2006). Remote Target Monitoring in Embedded Systems Lab Courses using a Sensor Network. In The 32nd Annual Conference of the IEEE Industrial Society - IECON’2006 (pp. 5433–5438). http://hdl.handle.net/20.500.12708/51521
• Embedded Systems Home Experimentation / Elmenreich, W., Trödhandl, C., & Weiss, B. (2006). Embedded Systems Home Experimentation. In Proceedings of the Second International Conference on Education and Technology (pp. 11–15). http://hdl.handle.net/20.500.12708/51520
• Embedded Systems Exams With True/False Questions: A Case Study / Gridling, G., Weiss, B., Elmenreich, W., & Trödhandl, C. (2006). Embedded Systems Exams With True/False Questions: A Case Study. In Proceedings of the Second International Conference on Education and Technology (pp. 168–172). http://hdl.handle.net/20.500.12708/51519
• Automatic Parameter Identification in FlexRay Based Automotive Communication Networks / Armengaud, E., & Steininger, A. (2006). Automatic Parameter Identification in FlexRay Based Automotive Communication Networks. In 11th IEEE International Conference on Emerging Technologies and Factory Automation (pp. 897–904). http://hdl.handle.net/20.500.12708/51518
  Projects: EXTRACT (2005–2008) / STEACS (2003–2008)
• Pushing the Limits of Remote Online Diagnosis in FlexRay Networks / Armengaud, E., & Steininger, A. (2006). Pushing the Limits of Remote Online Diagnosis in FlexRay Networks. In 6th IEEE International Workshop on Factory Communication Systems. IEEE International Workshop on Factory Communication Systems, Porto, Portugal, Austria. http://hdl.handle.net/20.500.12708/51517
  Project: EXTRACT (2005–2008)
• A Remote and Transparent Approach for the Test and Diagnosis of Automotive Networks / Armengaud, E., & Steininger, A. (2006). A Remote and Transparent Approach for the Test and Diagnosis of Automotive Networks. In Junior Scientist Conference 2006. Junior Scientist Conference, Wien, Austria. http://hdl.handle.net/20.500.12708/51516
  Project: EXTRACT (2005–2008)
• Low Level Bus Traffic Replay for the Test of Time-Triggered Communication Systems / Armengaud, E. (2006). Low Level Bus Traffic Replay for the Test of Time-Triggered Communication Systems. In 9th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (pp. 155–156). http://hdl.handle.net/20.500.12708/51515
  Project: EXTRACT (2005–2008)
• ExTraCT: A New Approach for the Transparent Test of Time-Triggered Communication Systems / Armengaud, E. (2006). ExTraCT: A New Approach for the Transparent Test of Time-Triggered Communication Systems. In 18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen. 18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Titisee, EU. http://hdl.handle.net/20.500.12708/51514
  Project: EXTRACT (2005–2008)
• VLSI Implementation of a Fault-Tolerant Distributed Clock Generation / Ferringer, M., Fuchs, G., Steininger, A., & Kempf, G. (2006). VLSI Implementation of a Fault-Tolerant Distributed Clock Generation. In The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (pp. 563–571). http://hdl.handle.net/20.500.12708/51509
  Project: DARTS (2005–2010)
• Fault-Tolerant Algorithms on SoCs - A case study / Steininger, A., Függer, M., Schmid, U., & Fuchs, G. (2006). Fault-Tolerant Algorithms on SoCs - A case study. In Supplement Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN) (pp. 190–191). http://hdl.handle.net/20.500.12708/51508
  Project: DARTS (2005–2010)
• Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip / Függer, M., Schmid, U., Fuchs, G., & Kempf, G. (2006). Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip. In EDCC-6 (pp. 87–96). http://hdl.handle.net/20.500.12708/51507
  Project: DARTS (2005–2010)
• Threshold Modules -- Die Schlüsselelemente zur Verteilten Generierung eines Fehlertoleranten Taktes / Fuchs, G., Grahsl, J., Schmid, U., Steininger, A., & Kempf, G. (2006). Threshold Modules -- Die Schlüsselelemente zur Verteilten Generierung eines Fehlertoleranten Taktes. In Austrochip Mikroelektroniktagung (pp. 149–156). http://hdl.handle.net/20.500.12708/51506
  Project: DARTS (2005–2010)
• An Efficient Test for a Transition Signalling based Up-/Down-Counter / Függer, M., Handl, T., Steininger, A., Widder, J., & Tögel, C. (2006). An Efficient Test for a Transition Signalling based Up-/Down-Counter. In Austrochip Mikroelektroniktagung (pp. 55–62). http://hdl.handle.net/20.500.12708/51505
  Project: DARTS (2005–2010)
• Testing the Hardware Implementation of a Distributed Clock Generation Algorithm for SoCs / Steininger, A., Handl, T., Fuchs, G., & Zangerl, F. (2006). Testing the Hardware Implementation of a Distributed Clock Generation Algorithm for SoCs. In East-West Design & Test International Workshop (pp. 59–64). http://hdl.handle.net/20.500.12708/51504
  Project: DARTS (2005–2010)
• Analysis of Constraints in a Fault-Tolerant Distributed Clock Generation Scheme / Fuchs, G., Függer, M., Steininger, A., & Zangerl, F. (2006). Analysis of Constraints in a Fault-Tolerant Distributed Clock Generation Scheme. In WDES 2006 3rd Workshop on Dependable Embedded Systems (pp. 22–27). http://hdl.handle.net/20.500.12708/51503
  Project: DARTS (2005–2010)
• A Reconfigurable Generic Dual-Core Architecture / Kottke, T., & Steininger, A. (2006). A Reconfigurable Generic Dual-Core Architecture. In Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN) (pp. 45–54). http://hdl.handle.net/20.500.12708/51502
• Ein dynamisch rekonfigurierbarer superskalarer Prozessor mit den Modi Sicherheit und Performanz / Steininger, A., & Kottke, T. (2006). Ein dynamisch rekonfigurierbarer superskalarer Prozessor mit den Modi Sicherheit und Performanz. In 18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (pp. 36–40). http://hdl.handle.net/20.500.12708/51501
• Teaching Hardware Software Codesign to Software Engineers / Delvai, M., & Steininger, A. (2006). Teaching Hardware Software Codesign to Software Engineers. In International Workshop on Reconfigurable Computing Education. 1st International Workshop on Reconfigurable Computing Education, Karlsruhe, EU. http://hdl.handle.net/20.500.12708/51473
• An Intelligent Interference-Minimizing Routing Algorithm / Hendling, K., Losert, T., & Jandl, M. (2006). An Intelligent Interference-Minimizing Routing Algorithm. In W. Huber (Ed.), Intelligent Systems at the Service of Mankind - Volume II (pp. 187–204). Ubooks. http://hdl.handle.net/20.500.12708/25007
• A CORBA-Based Architecture for Hard Real-Time Systems / Losert, T., Huber, W., Hendling, K., & Jandl, M. (2006). A CORBA-Based Architecture for Hard Real-Time Systems. In Intelligent Systems at the Service of Mankind - Volume II (pp. 239–254). Ubooks. http://hdl.handle.net/20.500.12708/25006

2005

• Dependable Embedded Systems Research at TU Vienna / Kopetz, H., Obermaisser, R., & Schmid, U. (2005). Dependable Embedded Systems Research at TU Vienna. Elektrotechnik Und Informationstechnik : E & i, 122(1), 33–37. https://doi.org/10.1007/BF03054020
• Small PC-Network Simulation -- A Comprehensive Performance Case Study / Albeseder, D., Függer, M., Breitenecker, F., Löscher, T., & Tauböck, S. M. (2005). Small PC-Network Simulation -- A Comprehensive Performance Case Study. Simulation News Europe, 44/45, 26–32. http://hdl.handle.net/20.500.12708/173433
• ASPEAR - An Asynchronous 16 Bit RISC Processor Core / Delvai, M., & Steininger, A. (2005). ASPEAR - An Asynchronous 16 Bit RISC Processor Core. Siemens PSE Technology Day, Vienna, Austria, Austria. http://hdl.handle.net/20.500.12708/84458
• Implementing Reliable Distributed Real Time Systems with the Theta Model / Hermant, J.-F., & Widder, J. (2005). Implementing Reliable Distributed Real Time Systems with the Theta Model. In 9th International Conference on Principles of Distributed Systems (pp. 259–271). http://hdl.handle.net/20.500.12708/51175
• A Method for Bit Level Test and Diagnosis of Communication Services / Armengaud, E., Steininger, A., & Horauer, M. (2005). A Method for Bit Level Test and Diagnosis of Communication Services. In Proceedings of IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS) 2005 (pp. 69–74). http://hdl.handle.net/20.500.12708/51174
  Project: STEACS (2003–2008)
• A Flexible Hardware Architecture for Fast Access on Large Non-Volatile Memories / Armengaud, E., Rothensteiner, F., Steininger, A., & Horauer, M. (2005). A Flexible Hardware Architecture for Fast Access on Large Non-Volatile Memories. In Proceedings of IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS) 2005 (pp. 113–120). http://hdl.handle.net/20.500.12708/51172
  Project: STEACS (2003–2008)
• A System for Automatic Testing of Embedded Software in Undergraduate Study Exercises / Legourski, V., Trödhandl, C., & Weiss, B. (2005). A System for Automatic Testing of Embedded Software in Undergraduate Study Exercises. In Proceedings Workshop on Embedded Systems Education (WESE’05) (pp. 44–51). http://hdl.handle.net/20.500.12708/51170
• On the Possibility of Consensus in Asynchronous Systems with Finite Average Response Times / Fetzer, C., Süßkraut, M., & Schmid, U. (2005). On the Possibility of Consensus in Asynchronous Systems with Finite Average Response Times. In On the Possibility of Consensus in Asynchronous Systems with Finite Average Response Times (pp. 271–280). IEEE Computer Society. http://hdl.handle.net/20.500.12708/51169
• Proof-Based Systems Engineering in ASSERT / Le Lann, G., & Schmid, U. (2005). Proof-Based Systems Engineering in ASSERT. In Proof-Based Systems Engineering in ASSERT. Data Systems in Aerospace, Edinburgh, EU. http://hdl.handle.net/20.500.12708/51168
• An Efficient Test and Diagnosis Environment for Communication Controllers / Armengaud, E., Steininger, A., & Horauer, M. (2005). An Efficient Test and Diagnosis Environment for Communication Controllers. In Austrochip 2005. Austrochip, Graz, Austria, Austria. ??? http://hdl.handle.net/20.500.12708/51144
  Project: STEACS (2003–2008)
• A Generic Tool for Systematic Tests in Embedded Automotive Communication Systems / Pallierer, R., Horauer, M., Zauner, M., Steininger, A., Armengaud, E., & Rothensteiner, F. (2005). A Generic Tool for Systematic Tests in Embedded Automotive Communication Systems. In Embedded World 2005. unbekannt. http://hdl.handle.net/20.500.12708/51143
  Project: STEACS (2003–2008)
• A Structured Approach for the Systematic Test of Embedded Automotive Communication Systems / Armengaud, E., Rothensteiner, F., Steininger, A., Pallierer, R., Horauer, M., & Zauner, M. (2005). A Structured Approach for the Systematic Test of Embedded Automotive Communication Systems. In Proceedings International Test Conference 2005 (pp. 21–28). IEEE Computer Society. http://hdl.handle.net/20.500.12708/51142
  Project: STEACS (2003–2008)
• Design of an Asynchronous Microprocessor with Four-State Logic / Delvai, M., Fuchs, G., Handl, T., Huber, W., & Steininger, A. (2005). Design of an Asynchronous Microprocessor with Four-State Logic. In Austrochip 2005 (pp. 105–112). http://hdl.handle.net/20.500.12708/51134
• Designoptimierung eines Prozessors mit Eigenfehlererkennung / Kottke, T., & Steininger, A. (2005). Designoptimierung eines Prozessors mit Eigenfehlererkennung. In 16. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen; (pp. 55–59). http://hdl.handle.net/20.500.12708/51133
• Evaluation of Message Delay Correlation in Distributed Systems / Albeseder, D. (2005). Evaluation of Message Delay Correlation in Distributed Systems. In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (pp. 139–150). http://hdl.handle.net/20.500.12708/51132
• Voronoi supported communication in Wireless ad-hoc Networks / Stratil, H. (2005). Voronoi supported communication in Wireless ad-hoc Networks. In The 2nd International Symposium on Voronoi Diagrams in Science and Engineering (pp. 105–116). http://hdl.handle.net/20.500.12708/51131
• Fault Tolerant Topology Control with unreliable Failure Detectors / Stratil, H. (2005). Fault Tolerant Topology Control with unreliable Failure Detectors. In Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems (pp. 767–772). http://hdl.handle.net/20.500.12708/51130
• Distributed Construction of an Underlay in Wireless Networks / Stratil, H. (2005). Distributed Construction of an Underlay in Wireless Networks. In Proceedings of the Second European Workshop on Wireless Sensor Networks (pp. 176–187). http://hdl.handle.net/20.500.12708/51128
• A Case Study in Efficient Microcontroller Education / Weiss, B., Gridling, G., & Proske, M. (2005). A Case Study in Efficient Microcontroller Education. In Proceedings Workshop on Embedded Systems Education WESE 2005 (pp. 36–43). http://hdl.handle.net/20.500.12708/51127
• Topology Control for Fault-Tolerant Communication in Highly Dynamic Wireless Networks / Thallner, B., & Moser, H. (2005). Topology Control for Fault-Tolerant Communication in Highly Dynamic Wireless Networks. In Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (pp. 89–100). http://hdl.handle.net/20.500.12708/51126
• Proof-Based System Engineering Using a Virtual System Model / Biely, M., Le Lann, G., & Schmid, U. (2005). Proof-Based System Engineering Using a Virtual System Model. In Service Availability (pp. 164–179). http://hdl.handle.net/20.500.12708/51125
• Brief Announcement: On the Possibility and the Impossibility of Message-Driven Self-Stabilizing Failure Detection / Hutle, M., & Widder, J. (2005). Brief Announcement: On the Possibility and the Impossibility of Message-Driven Self-Stabilizing Failure Detection. In Proceedings of the 24th ACM Symposium on Principles of Distributed Computing (p. 208). http://hdl.handle.net/20.500.12708/51124
• Failure Detection with Booting in Partially Synchronous Systems / Widder, J., Le Lann, G., & Schmid, U. (2005). Failure Detection with Booting in Partially Synchronous Systems. In Dependable Computing Conference - EDCC5 (pp. 20–37). http://hdl.handle.net/20.500.12708/51123
• On the Possibility and the Impossibility of Message-Driven Self-Stabilizing Failure Detection / Hutle, M., & Widder, J. (2005). On the Possibility and the Impossibility of Message-Driven Self-Stabilizing Failure Detection. In Self Stabilizing Systems (pp. 153–170). http://hdl.handle.net/20.500.12708/51122
• Self-Stabilizing Failure Detector Algorithms / Hutle, M., & Widder, J. (2005). Self-Stabilizing Failure Detector Algorithms. In IASTED International Conference on Parallel and Distributed Computing and Networks (pp. 485–490). http://hdl.handle.net/20.500.12708/51119
• Efficient Stimulus Genereation for Remote Testing of Distributed Systems - The Flexray Example / Armengaud, E., Steininger, A., & Horauer, M. (2005). Efficient Stimulus Genereation for Remote Testing of Distributed Systems - The Flexray Example. In Proceedings of the 10th IEEE Internationla Conference on Emerging Technologies and Factory Automation (pp. 763–770). IEEE. http://hdl.handle.net/20.500.12708/51082
  Project: STEACS (2003–2008)
• Design and Implementation of an Efficient Stack Machine / Schöberl, M. (2005). Design and Implementation of an Efficient Stack Machine. In Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International (IPDPS) (p. 159). http://hdl.handle.net/20.500.12708/51004
• Antrag UNI-Infrastruktur III, Embedded Systems Research Cluster / Schmid, U., Kopetz, H., Puschner, P., Mayerhofer, L., Steininger, A., Grünbacher, H., Kastner, W., & Krall, A. (2005). Antrag UNI-Infrastruktur III, Embedded Systems Research Cluster. http://hdl.handle.net/20.500.12708/33035

2004

• Constant Multiplication Methods / Tummeltshammer, P., Pueschel, M., Steininger, A., & Überhuber, C. W. (2004). Constant Multiplication Methods. http://hdl.handle.net/20.500.12708/33008
• Face Recognition on ASICs / Tummeltshammer, P., Pueschel, M., Steininger, A., & Überhuber, C. W. (2004). Face Recognition on ASICs. http://hdl.handle.net/20.500.12708/33009
• Why, Where and How to Use the Theta-Model / Widder, J. (2004). Why, Where and How to Use the Theta-Model. Seminaire Reflecs in INRIA Rocquencourt, Frankreich, INRIA Rocquencourt, Frankreich, Austria. http://hdl.handle.net/20.500.12708/84388
• VLSI Design and the Theta-Model (Kurzvorstellungen aktueller Forschung) / Widder, J. (2004). VLSI Design and the Theta-Model (Kurzvorstellungen aktueller Forschung). Diskussionskreis Fehlertoleranz, Berlin, Austria. http://hdl.handle.net/20.500.12708/84387
• The Theta-Model / Schmid, U. (2004). The Theta-Model. Diskussionskreis Fehlertoleranz, Berlin, Austria. http://hdl.handle.net/20.500.12708/84386
• The Theta-Model, and how to Boot Clock Synchronization in it / Widder, J. (2004). The Theta-Model, and how to Boot Clock Synchronization in it. Seminaire Reflecs in INRIA Rocquencourt, Frankreich, INRIA Rocquencourt, Frankreich, Austria. http://hdl.handle.net/20.500.12708/84385
• An FPGA based SoC Design for Testing Embedded Automotive Communication Systems employing the FlexRay Protocol / Horauer, M., Rothensteiner, F., Zauner, M., Armengaud, E., Steininger, A., Friedl, H., & Pallierer, R. (2004). An FPGA based SoC Design for Testing Embedded Automotive Communication Systems employing the FlexRay Protocol. In Austrochip 2004 (pp. 119–123). TU-Wien. http://hdl.handle.net/20.500.12708/50973
  Project: STEACS (2003–2008)
• An efficient implementation of the greedy forwarding strategy / Stratil, H. (2004). An efficient implementation of the greedy forwarding strategy. http://hdl.handle.net/20.500.12708/33012
• On the Possibility of Consensus in Asynchronous Systems with Finite Average Response Times / Fetzer, C., & Schmid, U. (2004). On the Possibility of Consensus in Asynchronous Systems with Finite Average Response Times. http://hdl.handle.net/20.500.12708/33010
• Distributed Construction of Sparse Fault-Tolerant Overlay Networks / Thallner, B., & Schmid, U. (2004). Distributed Construction of Sparse Fault-Tolerant Overlay Networks. http://hdl.handle.net/20.500.12708/33011
• Recovery Mechanisms for Dual Core Architectures / El Salloum, C., & Steininger, A. (2004). Recovery Mechanisms for Dual Core Architectures. http://hdl.handle.net/20.500.12708/33007
• A Reconfigurable Generic Dual Core Architecture / Kottke, T., & Steininger, A. (2004). A Reconfigurable Generic Dual Core Architecture. http://hdl.handle.net/20.500.12708/33006
• A Strategy for Experimental Fault Injection into an Asynchronous Processor / Rahbaran, B., & Steininger, A. (2004). A Strategy for Experimental Fault Injection into an Asynchronous Processor. http://hdl.handle.net/20.500.12708/33005
• Options for Remote Diagnosis in Automotive Distributed Networks / Steininger, A., Horauer, M., & Armengaud, E. (2004). Options for Remote Diagnosis in Automotive Distributed Networks. http://hdl.handle.net/20.500.12708/33004
  Project: STEACS (2003–2008)
• A Flexible Hardware Architecture for Fast Access on Large Non-Volatile Memories / Armengaud, E., Rothensteiner, F., Steininger, A., & Horauer, M. (2004). A Flexible Hardware Architecture for Fast Access on Large Non-Volatile Memories. http://hdl.handle.net/20.500.12708/33003
  Project: STEACS (2003–2008)
• Fault Injection -- Requirements and Concepts / Armengaud, E., Steininger, A., & Horauer, M. (2004). Fault Injection -- Requirements and Concepts. http://hdl.handle.net/20.500.12708/33002
  Project: STEACS (2003–2008)
• Fault Injection Method / Armengaud, E., & Steininger, A. (2004). Fault Injection Method. http://hdl.handle.net/20.500.12708/33001
  Project: STEACS (2003–2008)
• Accurate Diagnosis Method with Access to Bit-Level / Armengaud, E. (2004). Accurate Diagnosis Method with Access to Bit-Level. http://hdl.handle.net/20.500.12708/33000
  Project: STEACS (2003–2008)
• FlexRay Parameter Classification / Armengaud, E. (2004). FlexRay Parameter Classification. http://hdl.handle.net/20.500.12708/32999
  Project: STEACS (2003–2008)
• Automatic Parameter Detection for Communication Protocols / Armengaud, E., & Steininger, A. (2004). Automatic Parameter Detection for Communication Protocols. http://hdl.handle.net/20.500.12708/32998
  Project: STEACS (2003–2008)
• Monitoring and Replay Hardware -- Specification and Implementation / Armengaud, E., & Horauer, M. (2004). Monitoring and Replay Hardware -- Specification and Implementation. http://hdl.handle.net/20.500.12708/32997
  Project: STEACS (2003–2008)
• Monitoring and Replay hardware -- Requirements and Concepts / Armengaud, E., Steininger, A., & Horauer, M. (2004). Monitoring and Replay hardware -- Requirements and Concepts. http://hdl.handle.net/20.500.12708/32996
  Project: STEACS (2003–2008)
• Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods / Delvai, M., Steininger, A., & Huber, W. (2004). Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods. http://hdl.handle.net/20.500.12708/32995
• Code Alternation Logic (CAL): A Novel Efficient Design Approach for Delay-Insensitive Asynchronous Circuits / Steininger, A., Delvai, M., & Huber, W. (2004). Code Alternation Logic (CAL): A Novel Efficient Design Approach for Delay-Insensitive Asynchronous Circuits. http://hdl.handle.net/20.500.12708/32994
• Synchronous and Asynchronous Design Methods -- A Hardware Designer's Perspective / Steininger, A., Delvai, M., & Huber, W. (2004). Synchronous and Asynchronous Design Methods -- A Hardware Designer’s Perspective. http://hdl.handle.net/20.500.12708/32993
• Delay Insensitive Asychronous Pipeline Implementation for Code Alternation Logic / Huber, W., Steininger, A., & Delvai, M. (2004). Delay Insensitive Asychronous Pipeline Implementation for Code Alternation Logic. http://hdl.handle.net/20.500.12708/32992
• Code Alternation Logic -- A Novel and Efficient Method for Delay-Insensitive Asynchronous Circuits / Steininger, A., Delvai, M., & Huber, W. (2004). Code Alternation Logic -- A Novel and Efficient Method for Delay-Insensitive Asynchronous Circuits. http://hdl.handle.net/20.500.12708/32991
• DARTS - Distributed Algorithms for Robust Tick Synchronization / Fuchs, G., Schmid, U., & Steininger, A. (2004). DARTS - Distributed Algorithms for Robust Tick Synchronization. http://hdl.handle.net/20.500.12708/32990
• EPOCAL - Exploring the Potential of Code Alternation Logic / Steininger, A., Handl, T., & Fuchs, G. (2004). EPOCAL - Exploring the Potential of Code Alternation Logic. http://hdl.handle.net/20.500.12708/32989
• Dezentrale Fehlertolerante Taktgenerierung in VLSI Chips / Schmid, U., & Steininger, A. (2004). Dezentrale Fehlertolerante Taktgenerierung in VLSI Chips. http://hdl.handle.net/20.500.12708/32988
• The usage of the Delaunay Triangulation (resp. the Voronoi Diagram) in dynamic wireless ad-hoc networks / Stratil, H. (2004). The usage of the Delaunay Triangulation (resp. the Voronoi Diagram) in dynamic wireless ad-hoc networks. http://hdl.handle.net/20.500.12708/32987
• Distributed Construction of Fault-Tolerant Overlay Networks: Construction Algorithm / Moser, H., & Thallner, B. (2004). Distributed Construction of Fault-Tolerant Overlay Networks: Construction Algorithm. http://hdl.handle.net/20.500.12708/32985
• Performing Automatic Physical Injection of Signal-Flips and Delay Faults with the toolset FIDYCO / Rahbaran, B. (2004). Performing Automatic Physical Injection of Signal-Flips and Delay Faults with the toolset FIDYCO. http://hdl.handle.net/20.500.12708/32986
• Distributed Construction of Fault-Tolerant Overlay Networks: Propose Modules / Thallner, B. (2004). Distributed Construction of Fault-Tolerant Overlay Networks: Propose Modules. http://hdl.handle.net/20.500.12708/32984
• On the Possibility and the Impossibility of Time Free Self-Stabilizing Failure Detection / Hutle, M., & Widder, J. (2004). On the Possibility and the Impossibility of Time Free Self-Stabilizing Failure Detection. http://hdl.handle.net/20.500.12708/32983
• Time Free Self-Stabilizing Local Failure Detection / Hutle, M., & Widder, J. (2004). Time Free Self-Stabilizing Local Failure Detection. http://hdl.handle.net/20.500.12708/32982
• Implementing Time Free Designs for Distributed Real-Time Systems (A Case Study) / Hermant, J.-F., & Widder, J. (2004). Implementing Time Free Designs for Distributed Real-Time Systems (A Case Study). http://hdl.handle.net/20.500.12708/32981
• Final Report START-Project Y41 / Schmid, U. (2004). Final Report START-Project Y41. http://hdl.handle.net/20.500.12708/32980
• Ein Verfahren für das verteilte Generieren eines fehlertoleranten adaptiven Taktes in Hardware / Fuchs, G., Schmid, U., & Steininger, A. (2004). Ein Verfahren für das verteilte Generieren eines fehlertoleranten adaptiven Taktes in Hardware. http://hdl.handle.net/20.500.12708/32979
  Project: DARTS (2005–2010)
• Fault-Tolerant Distributed Algorithms in Sparse Ad Hoc Wireless Networks / Schmid, U., & Weiss, B. (2004). Fault-Tolerant Distributed Algorithms in Sparse Ad Hoc Wireless Networks. http://hdl.handle.net/20.500.12708/32977
• Design of a Voronoi-Aided Routing (VAR) Protocol for Wireless Sensor Networks / Stratil, H. (2004). Design of a Voronoi-Aided Routing (VAR) Protocol for Wireless Sensor Networks. http://hdl.handle.net/20.500.12708/32978
• Die Wichtigsten Kommandos in der dc_shell(synopsys) / Rahbaran, B. (2004). Die Wichtigsten Kommandos in der dc_shell(synopsys). http://hdl.handle.net/20.500.12708/32976
• Failure Model Coverage under Transient Link Failures / Schmid, U. (2004). Failure Model Coverage under Transient Link Failures. http://hdl.handle.net/20.500.12708/32975
• Synchronous Byzantine Agreement under Hybrid Process and Link Failures / Schmid, U., & Weiss, B. (2004). Synchronous Byzantine Agreement under Hybrid Process and Link Failures. http://hdl.handle.net/20.500.12708/32974
• Creating and Grading Multiple-Choice Exams / Weiss, B., & Gridling, G. (2004). Creating and Grading Multiple-Choice Exams. http://hdl.handle.net/20.500.12708/32943

2003

• A Generic Architecture for Integrated Smart Transducers / Delvai, M., Eisenmann, U., & Elmenreich, W. (2003). A Generic Architecture for Integrated Smart Transducers. Lecture Notes in Computer Science, 2778, 733–744. http://hdl.handle.net/20.500.12708/174844
• Dealing With Dormant Faults in an Embedded Fault-Tolerant Computer System / Scherrer, C., & Steininger, A. (2003). Dealing With Dormant Faults in an Embedded Fault-Tolerant Computer System. IEEE Transactions on Reliability, 52(4), 512–522. http://hdl.handle.net/20.500.12708/174825
• A Transparent Online Memory Test for Simultaneous Detection of Functional Faults and Soft Errors in Memories / Thaller, K., & Steininger, A. (2003). A Transparent Online Memory Test for Simultaneous Detection of Functional Faults and Soft Errors in Memories. IEEE Transactions on Reliability, 52(4), 413–422. http://hdl.handle.net/20.500.12708/174824
• A Generic Architecture for Integrated Smart Transducers / Delvai, M., Eisenmann, U., & Elmenreich, W. (2003). A Generic Architecture for Integrated Smart Transducers. International Conference, FPL 2003, Lissabon, Portugal, Austria. http://hdl.handle.net/20.500.12708/84208
• Perfect failure detection with booting in partially synchronous systems / Widder, J., Le Lann, G., & Schmid, U. (2003). Perfect failure detection with booting in partially synchronous systems. http://hdl.handle.net/20.500.12708/32910
• Booting clock synchronization in partially synchronous systems with hybrid node and link failures. / Widder, J., & Schmid, U. (2003). Booting clock synchronization in partially synchronous systems with hybrid node and link failures. http://hdl.handle.net/20.500.12708/32911
• Impossibility results and lower bounds for consensus under link failures. / Schmid, U., & Weiss, B. (2003). Impossibility results and lower bounds for consensus under link failures. http://hdl.handle.net/20.500.12708/32908
• Fault tolerant communication topologies for wireless ad hoc networks / Thallner, B., & Schmid, U. (2003). Fault tolerant communication topologies for wireless ad hoc networks. http://hdl.handle.net/20.500.12708/32909
• Towards an optimal algorithm for hybrid Byzantine agreement. / Biely, M. (2003). Towards an optimal algorithm for hybrid Byzantine agreement. http://hdl.handle.net/20.500.12708/32904
• Simulation von Signalen selbstdefinierten Typs in verschiedenen Stufen des Design-Flows / Huber, W., & Handl, T. (2003). Simulation von Signalen selbstdefinierten Typs in verschiedenen Stufen des Design-Flows. http://hdl.handle.net/20.500.12708/32899
• Projektbericht Technische Informatik: Seamless Campus / Vilanek, J., Schmid, U., Kastner, W., Weiss, B., Puschner, P., Elmenreich, W., Deinhart, H., & Meyer, W. (2003). Projektbericht Technische Informatik: Seamless Campus. http://hdl.handle.net/20.500.12708/32898

2002

• Peripherieanbindung an SPEAR Extension Modules / Huber, W. (2002). Peripherieanbindung an SPEAR Extension Modules. http://hdl.handle.net/20.500.12708/32849
• Handbuch für SPEAR (Scalable Processor for Embedded Applications in Real-Time Environments) / Delvai, M. (2002). Handbuch für SPEAR (Scalable Processor for Embedded Applications in Real-Time Environments). http://hdl.handle.net/20.500.12708/32848
• Zutrittskontrolle und Überwachung der Laborräume des Instituts für Technische Informatik / Vilanek, J. (2002). Zutrittskontrolle und Überwachung der Laborräume des Instituts für Technische Informatik. http://hdl.handle.net/20.500.12708/32800

2001

• Message-efficient consensus in presence of hybrid node and link faults / Biely, M., & Schmid, U. (2001). Message-efficient consensus in presence of hybrid node and link faults. http://hdl.handle.net/20.500.12708/32915

2023

• Comprehensive Characterization of Consensus Solvability in Dynamic Networks with Transient Stability / Pacheiner, P. (2023). Comprehensive Characterization of Consensus Solvability in Dynamic Networks with Transient Stability [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2023.86340
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• go2async: A high-level synthesis tool for asynchronous circuits based on click-elements / Wiedemann, S. M. (2023). go2async: A high-level synthesis tool for asynchronous circuits based on click-elements [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2023.97424
  Download: PDF (1.93 MB)

2022

• Evaluation of different tools for design and fault-injection of asynchronous circuits / Schwendinger, M. (2022). Evaluation of different tools for design and fault-injection of asynchronous circuits [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2022.98624
  Download: PDF (2.31 MB)
• Beta-CIDM: A faithful and composable delay model with adversarial noise / Öhlinger, D. (2022). Beta-CIDM: A faithful and composable delay model with adversarial noise [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2022.87144
  Download: PDF (1.81 MB)
• Smart SoC testing and remote configuration facilitated by the use of IJTAG complemented with on-chip microprocessor access / Pircher, C. (2022). Smart SoC testing and remote configuration facilitated by the use of IJTAG complemented with on-chip microprocessor access [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2022.98141
  Download: PDF (1.19 MB)
• Fault-tolerant GALS architecture based on pausable clocking / Dür, W. (2022). Fault-tolerant GALS architecture based on pausable clocking [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2022.88760
  Download: PDF (4.17 MB)

2021

• Proper abstractions for digital electronic circuits: A physically guided approach / Maier, J. (2021). Proper abstractions for digital electronic circuits: A physically guided approach [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2022.102506
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• On the strongest message adversary for directed dynamic networks / Felber, S. (2021). On the strongest message adversary for directed dynamic networks [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2022.87145
  Download: PDF (996 KB)
• IoT implementation and evaluation of distributed consensus algorithms / Echtinger-Sieghart, C. (2021). IoT implementation and evaluation of distributed consensus algorithms [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2021.85743
  Download: PDF (2.56 MB)
• Quantitative Comparison of the sensitivity of delay-insensitive design templates to transient faults / Behal, P. (2021). Quantitative Comparison of the sensitivity of delay-insensitive design templates to transient faults [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2021.81601
  Download: PDF (2.18 MB)
• Implementations, improvements & implications of hardware-assisted CFG-based control flow integrity schemes / Telesklav, M. (2021). Implementations, improvements & implications of hardware-assisted CFG-based control flow integrity schemes [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2021.72945
  Download: PDF (2.71 MB)

2020

• An Extension framework for epistemic reasoning in Byzantine distributed systems / Schlögl, T. (2020). An Extension framework for epistemic reasoning in Byzantine distributed systems [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2020.69444
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• Automatic competitive analysis of real-time scheduling algorithms for firm-deadline tasks with non-preemptible sections and precedence constraints / Schaumberger, N. (2020). Automatic competitive analysis of real-time scheduling algorithms for firm-deadline tasks with non-preemptible sections and precedence constraints [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2020.70863
  Download: PDF (871 KB)

2019

• Fault-tolerant clock distribution in grid-like networks / Perner, M. (2019). Fault-tolerant clock distribution in grid-like networks [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2019.72064
  Download: PDF (9.22 MB)
• Fault masking in synchronous and in asynchronous logic - a comparsion / Ramsl, W. (2019). Fault masking in synchronous and in asynchronous logic - a comparsion [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2019.25573
  Download: PDF (1.19 MB)

2018

• Operation and verification framework for the FRad experimental ASIC / Fritz, B. (2018). Operation and verification framework for the FRad experimental ASIC [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2018.23746
  Download: PDF (3.38 MB)
• Agreement algorithms in directed dynamic networks / Schwarz, M. (2018). Agreement algorithms in directed dynamic networks [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2018.57089
  Download: PDF (1.29 MB)
• Knowledge and communication complexity in distributed systems / Pfleger, D. (2018). Knowledge and communication complexity in distributed systems [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2018.40116
  Download: PDF (993 KB)
• SoC FPGA Oszilloskop : Implementierung eines Oszilloskops auf einem FPGA mit eingebettetem Prozessor / Obermüller, J. (2018). SoC FPGA Oszilloskop : Implementierung eines Oszilloskops auf einem FPGA mit eingebettetem Prozessor [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/80024

2017

• COTS FPGAs in space : From old concerns to new possibilities / Schütz, M. (2017). COTS FPGAs in space : From old concerns to new possibilities [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2017.54551
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• Temporal-epistemic logic in Byzantine message-passing contexts / Fimml, P. (2017). Temporal-epistemic logic in Byzantine message-passing contexts [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2017.38943
  Download: PDF (858 KB)
• Design of custom ASIC for radiation experiments to study single event effects / Savulimedu Veeravalli, V. (2017). Design of custom ASIC for radiation experiments to study single event effects [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2017.48221
  Download: PDF (74.4 MB)
• Protecting 4-phase delay-insensitive communication against transient faults / Huemer, F. F. (2017). Protecting 4-phase delay-insensitive communication against transient faults [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2017.30269
  Download: PDF (906 KB)

2016

• ASCARTS - design of an asynchronous processor using a high-level specification language / Hermann, C. (2016). ASCARTS - design of an asynchronous processor using a high-level specification language [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2016.21820
  Download: PDF (572 KB)

2015

• Parameterized model checking of fault-tolerant distributed algorithms / Gmeiner, A. (2015). Parameterized model checking of fault-tolerant distributed algorithms [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2015.33793
  Download: PDF (1.92 MB)
• Realizing negative introspection into justification logic : proof-theoretic approach / Borg, A. (2015). Realizing negative introspection into justification logic : proof-theoretic approach [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2015.29804
  Download: PDF (564 KB)

2014

• Composability for fail-safe safety-critical systems / Resch, S. (2014). Composability for fail-safe safety-critical systems [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2014.27500
  Download: PDF (1.48 MB)
• Efficient interfacing between timing domains / Kutschera, R. (2014). Efficient interfacing between timing domains [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2014.25542
  Download: PDF (3.5 MB)
• Selection and hardware-implementation of an efficient consensus algorithm for a mesochronous system / Heinisch, A. (2014). Selection and hardware-implementation of an efficient consensus algorithm for a mesochronous system [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2014.22245
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• Real-time performance analysis of synchronous distributed systems / Kößler, A. (2014). Real-time performance analysis of synchronous distributed systems [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2014.22342
  Download: PDF (3.45 MB)
• Effekte von Stuck-At Faults in Delay-Insensitiver Logik / Trenkwalder, C. (2014). Effekte von Stuck-At Faults in Delay-Insensitiver Logik [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2014.26284
  Download: PDF (3.98 MB)
• Online test vector insertion - a concurrent built-in self-testing (CBIST) approach for asynchronous logic / Maier, J. (2014). Online test vector insertion - a concurrent built-in self-testing (CBIST) approach for asynchronous logic [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2014.25295
  Download: PDF (1.78 MB)
• Building robust GALS circuits : fault-tolerant and variation-aware design. Techniques for reliable circuit operation / Lechner, J. (2014). Building robust GALS circuits : fault-tolerant and variation-aware design. Techniques for reliable circuit operation [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2014.25096
  Download: PDF (1.77 MB)

2013

• Analysis of the failure behavior of memory management units / Hechinger, O. (2013). Analysis of the failure behavior of memory management units [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2013.23180
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• A non-blocking fault-tolerant asynchronous networks-on-chip router / Naqvi, S. R. (2013). A non-blocking fault-tolerant asynchronous networks-on-chip router [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2013.22599
  Download: PDF (2.62 MB)
• Solving k-Set agreement in dynamic networks / Schwarz, M. (2013). Solving k-Set agreement in dynamic networks [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2013.21843
  Download: PDF (675 KB)
• Self-stabilizing Byzantine fault-tolerant clock distribution in grids / Perner, M. (2013). Self-stabilizing Byzantine fault-tolerant clock distribution in grids [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2013.21901
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• A digital metastability model for VLSI circuits / Polzer, T. (2013). A digital metastability model for VLSI circuits [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2013.22620
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• Easy impossibility proofs for k-set agreement / Winkler, K. (2013). Easy impossibility proofs for k-set agreement [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2013.22720
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• Solving the labeling problem : a Byzantine fault-tolerant self-stabilizing FPGA prototype based on the FATAL+ protocol / Hofstätter, M. (2013). Solving the labeling problem : a Byzantine fault-tolerant self-stabilizing FPGA prototype based on the FATAL+ protocol [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2013.21760
  Download: PDF (1.62 MB)
• Design and evaluation of an AXI4 bus system / Pados, K. D. (2013). Design and evaluation of an AXI4 bus system [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/159734
• Performance aware hardware runtime monitors / Hagmann, A. (2013). Performance aware hardware runtime monitors [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/159732
• Analoge Q-Control zur Güteverstärkung von piezoelektrischen MEMS Resonatoren / Hofbauer, F. (2013). Analoge Q-Control zur Güteverstärkung von piezoelektrischen MEMS Resonatoren [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/159679

2012

• Asynchronous logic in real-time systems / Ferringer, M. (2012). Asynchronous logic in real-time systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-46960
  Download: PDF (1.83 MB)
• Elaboration of a Fault-tolerance strategy for space-borne digital signal processing applications / Fuchs, B. (2012). Elaboration of a Fault-tolerance strategy for space-borne digital signal processing applications [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-46481
  Download: PDF (4.69 MB)
• Self-healing asynchronous circuits for high-reliability applications / Panhofer, T. (2012). Self-healing asynchronous circuits for high-reliability applications [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-47033
  Download: PDF (1.52 MB)
• Selbststabilisierende byzantinisch fehlertolerante Takterzeugung in FPGAs / Posch, M. (2012). Selbststabilisierende byzantinisch fehlertolerante Takterzeugung in FPGAs [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/160584
• Implementation of a distributed computation framework / Pavlovic, M. (2012). Implementation of a distributed computation framework [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/159720

2011

• Effects and mitigation of transient faults in quasi delay-insensitive logic / Friesenbichler, W. (2011). Effects and mitigation of transient faults in quasi delay-insensitive logic [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-48162
  Download: PDF (2.41 MB)
• SPEAR2C : implementation of a cache controller for SPEAR2 / Birner, M. (2011). SPEAR2C : implementation of a cache controller for SPEAR2 [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-59473
  Download: PDF (7.43 MB)
• Hardware description with timing requirements / Resch, S. (2011). Hardware description with timing requirements [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-48081
  Download: PDF (963 KB)
• Description methods for asynchronous circuits : a comparison / Najvirt, R. (2011). Description methods for asynchronous circuits : a comparison [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-41766
  Download: PDF (688 KB)
• Implementation of the TTP/A protocol and WCET analysis on the SPEAR2 platform / Burker, A. (2011). Implementation of the TTP/A protocol and WCET analysis on the SPEAR2 platform [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/160444
• The SPEAR2 Hardware/Software Interface / Walter, M. (2011). The SPEAR2 Hardware/Software Interface [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/159954

2010

• Analysis of on-chip fault-tolerant distributed algorithms / Függer, M. (2010). Analysis of on-chip fault-tolerant distributed algorithms [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-39917
  Download: PDF (1.45 MB)
• Topology in Distributed Computing / Nowak, T. (2010). Topology in Distributed Computing [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-30814
  Download: PDF (492 KB)
• Weak system models for fault-tolerant distributed agreement problems / Robinson, P. (2010). Weak system models for fault-tolerant distributed agreement problems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-42017
  Download: PDF (956 KB)
• Generic microprocessor-controlled test unit / Hofer, M. (2010). Generic microprocessor-controlled test unit [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/159779

2009

• A model for distributed computing in real-time systems / Moser, H. (2009). A model for distributed computing in real-time systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-29073
  Download: PDF (856 KB)
• Fault-tolerant distributed algorithms for on-chip tick generation: concepts, implementations and evaluations / Fuchs, G. (2009). Fault-tolerant distributed algorithms for on-chip tick generation: concepts, implementations and evaluations [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-33442
  Download: PDF (2.51 MB)
• Fault-tolerant hardware implementation of a consensus algorithm / Polzer, T. (2009). Fault-tolerant hardware implementation of a consensus algorithm [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-37200
  Download: PDF (2.22 MB)
• Mapping stereo matching algorithms to hardware / Ambrosch, K. (2009). Mapping stereo matching algorithms to hardware [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-29639
  Download: PDF (11.6 MB)
• High-level system modeling with SystemC and TLM / Widtmann, C. (2009). High-level system modeling with SystemC and TLM [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-25914
  Download: PDF (4.69 MB)
• Analysis of common cause faults in dual core architectures / Tummeltshammer, P. (2009). Analysis of common cause faults in dual core architectures [Dissertation, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/186533
• Automated regression testing of embedded devices / Jahn, P. (2009). Automated regression testing of embedded devices [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/186055
• Dynamic aspects of modelling distributed computations / Biely, M. (2009). Dynamic aspects of modelling distributed computations [Dissertation, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/184232

2008

• SPEAR2 - an improved version of SPEAR / Fletzer, M. (2008). SPEAR2 - an improved version of SPEAR [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-19088
  Download: PDF (766 KB)
• A transparent online test approach for time-triggered communication protocols / Armengaud, E. (2008). A transparent online test approach for time-triggered communication protocols [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-23226
  Download: PDF (1.59 MB)
• AMBA4SPEAR2: an AMBA extension module for the SPEAR2 processor core / Mosser, J. (2008). AMBA4SPEAR2: an AMBA extension module for the SPEAR2 processor core [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-27846
  Download: PDF (8.34 MB)
• Self-oscillation as a time-reference in asynchronous logic - the UART example / Klein, W. (2008). Self-oscillation as a time-reference in asynchronous logic - the UART example [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-20396
  Download: PDF (980 KB)
• Optimization of FSL gates / Jeitler, M. (2008). Optimization of FSL gates [Master Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/183557
• Implementation of a design tool for generation of FSL circuits / Lechner, J. (2008). Implementation of a design tool for generation of FSL circuits [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/182090

2007

• Simulation and performance evaluation of a topology control algorithm in NS2 / Walter, C. (2007). Simulation and performance evaluation of a topology control algorithm in NS2 [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-14919
  Download: PDF (3.5 MB)
• Reconfigurable hardware implementation of polynomial arithmetic over the finite field GF(3) / Prokop, H. (2007). Reconfigurable hardware implementation of polynomial arithmetic over the finite field GF(3) [Master Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/178009

2006

• Advantages and limitations of position-based communication in wireless ad-hoc networks / Stratil, H. (2006). Advantages and limitations of position-based communication in wireless ad-hoc networks [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-14382
  Download: PDF (703 KB)
• Fault-tolerant distributed clock generation in VLSI systems-on-chip / Függer, M. (2006). Fault-tolerant distributed clock generation in VLSI systems-on-chip [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-28679
  Download: PDF (462 KB)
• Analyse der Implementierbarkeit einer aktiven Schallunterdrückungslösung in Hardware / Varga, C. (2006). Analyse der Implementierbarkeit einer aktiven Schallunterdrückungslösung in Hardware [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-32417
  Download: PDF (6.32 MB)
• Oszillatorische Blutdruckmessung für Patienten mit Rotationsblutpumpen / Krupnik, L. (2006). Oszillatorische Blutdruckmessung für Patienten mit Rotationsblutpumpen [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/186913
• An asynchronous hardware design for distributed tick generation / Ferringer, M. (2006). An asynchronous hardware design for distributed tick generation [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/179556

2005

• Distributed construction of a fault-tolerant wireless communication topology for networked embedded systems oder "Implementing the Thallner-algorithm" / Moser, H. (2005). Distributed construction of a fault-tolerant wireless communication topology for networked embedded systems oder “Implementing the Thallner-algorithm” [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-12392
  Download: PDF (461 KB)
• Failure detection in sparse networks / Hutle, M. (2005). Failure detection in sparse networks [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-21522
  Download: PDF (580 KB)
• Design of an asynchronous processor based on code alternation logic - exploration of delay insensitivity / Huber, W. (2005). Design of an asynchronous processor based on code alternation logic - exploration of delay insensitivity [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-18234
  Download: PDF (7.47 MB)
• JOP: a Java optimized processor for embedded real-time systems / Schöberl, M. (2005). JOP: a Java optimized processor for embedded real-time systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-9003
  Download: PDF (9.56 MB)
• Revision and verification of an enhanced UART / Gallo, R. (2005). Revision and verification of an enhanced UART [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/180580
• Topology control for fault-tolerant communication in wireless ad hoc networks / Thallner, B. (2005). Topology control for fault-tolerant communication in wireless ad hoc networks [Dissertation, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/180401
• Untersuchung von fehlertoleranten Prozessorarchitekturen für sicherheitsrelevante Automobilanwendungen / Kottke, T. (2005). Untersuchung von fehlertoleranten Prozessorarchitekturen für sicherheitsrelevante Automobilanwendungen [Dissertation, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/177711
• An experimental comparison of robustness between synchronous and asynchronous logic design / Rahbaran, B. (2005). An experimental comparison of robustness between synchronous and asynchronous logic design [Dissertation, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/177677

2004

• Distributed computing in the presence of bounded asynchrony / Widder, J. (2004). Distributed computing in the presence of bounded asynchrony [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-13246
  Download: PDF (715 KB)
• Design of an asynchronous processor based on code alternation logic - treatment of non-linear data paths / Delvai, M. (2004). Design of an asynchronous processor based on code alternation logic - treatment of non-linear data paths [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-13195
  Download: PDF (7.37 MB)
• Multiple constant multiplication by time-multiplexed mapping of addition chains / Tummeltshammer, P. (2004). Multiple constant multiplication by time-multiplexed mapping of addition chains [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/184119
• Implementierung eines FPGA-basierten Hardware-Fehlerinjektors / Handl, T. (2004). Implementierung eines FPGA-basierten Hardware-Fehlerinjektors [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/184082
• Experimentelle Verifikation von Synchronitätsannahmen für Computernetzwerke / Albeseder, D. (2004). Experimentelle Verifikation von Synchronitätsannahmen für Computernetzwerke [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/181067

2003

• A superscalar 16 bit microcontroller for real-time applications / Fuchs, G. (2003). A superscalar 16 bit microcontroller for real-time applications [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-11271
  Download: PDF (1.85 MB)
• Xerxes error behavior / Rieder, B. (2003). Xerxes error behavior [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-10803
  Download: PDF (829 KB)
• Realisierung eines generischen Online Debuggers für Embedded Systems / El Salloum, C. (2003). Realisierung eines generischen Online Debuggers für Embedded Systems [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/185821
• Entwicklung eines USB fullspeed VHDL-Cores / Eggenhofer, M. (2003). Entwicklung eines USB fullspeed VHDL-Cores [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/183637
• Integrating time-triggered distributed system design in MATLAB/Simulink / Winkler, M. (2003). Integrating time-triggered distributed system design in MATLAB/Simulink [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/183455
• Asynchrone Realisierung einer Arithmetic Logic Unit / Pedram, T. (2003). Asynchrone Realisierung einer Arithmetic Logic Unit [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/183013

2002

• Switching on : how processes initialize for consistent broadcast / Widder, J. (2002). Switching on : how processes initialize for consistent broadcast [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-77756
  Download: PDF (212 KB)
• Byzantine agreement under the perception-based fault model / Biely, M. (2002). Byzantine agreement under the perception-based fault model [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-77933
  Download: PDF (356 KB)
• Topology management and routing in wireless networks : an overview / Stratil, H. (2002). Topology management and routing in wireless networks : an overview [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/186446
• Communication protocol test device in VHDL / Resanka, C. (2002). Communication protocol test device in VHDL [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/186234
• Realization of a re-usable offline debugger for the SPEAR micro-controller / Jankela, M. (2002). Realization of a re-usable offline debugger for the SPEAR micro-controller [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/185819
• Design and implementation of a highly efficient communication node for real-time applications / Eisenmann, U. (2002). Design and implementation of a highly efficient communication node for real-time applications [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/185224
• Comparison of protocol frameworks / Rahimi Movaghar, S. (2002). Comparison of protocol frameworks [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/181787
• Authenticated consensus / Weiss, B. (2002). Authenticated consensus [Dissertation, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/179189

2001

• A transparent online memory test / Thaller, K. (2001). A transparent online memory test [Dissertation, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/180075
• Zur Rolle der Verifikation im Designprozess digitaler integrierter Schaltungen / Vilanek, J. (2001). Zur Rolle der Verifikation im Designprozess digitaler integrierter Schaltungen [Dissertation, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/179306

• Josef Widder: FIT-IT Embedded Systems Dissertationsstipendium "Distributed Computing in the Presence of Bounded Asynchrony"
  2004 / Austria
• Ulrich Schmid: Synchronized Universal Time Coordinated for Distributed Real-Time Systems
  1997 / START-Programm / Austria
• Ulrich Schmid: Kardinal Innitzer Förderungspreis
  1995 / Kardinal-Innitzer-Preis / Austria

Soon, this page will include additional information such as reference projects, conferences, events, and other research activities.

Until then, please visit Embedded Computing Systems’ research profile in TISS .