Jakob Lechner
Univ.Lektor Dipl.-Ing. Dr.techn.
Role
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External Lecturer
Computer Engineering, E191
Publications
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State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration
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Schütz, M., Steininger, A., Huemer, F., & Lechner, J. (2018). State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/dft.2018.8602984
Project: Intel CARS (2017–2019) - A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes / Huemer, F., Lechner, J., & Steininger, A. (2016). A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes. In Proceedings 2016 IEEE International Conference on Computer Design (pp. 392–395). http://hdl.handle.net/20.500.12708/56881
- Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes / Lechner, J., Steininger, A., & Huemer, F. (2015). Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes. In 33rd IEEE International Conference on Computer Design (p. 8). http://hdl.handle.net/20.500.12708/56358
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Building robust GALS circuits : fault-tolerant and variation-aware design. Techniques for reliable circuit operation
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Lechner, J. (2014). Building robust GALS circuits : fault-tolerant and variation-aware design. Techniques for reliable circuit operation [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2014.25096
Download: PDF (1.77 MB) - Protection of Muller-Pipelines from transient faults / Naqvi, S. R., Lechner, J., & Steininger, A. (2014). Protection of Muller-Pipelines from transient faults. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA, Non-EU. https://doi.org/10.1109/isqed.2014.6783315
- An SET Tolerant Tree Arbiter Cell / Naqvi, S. R., Steininger, A., & Lechner, J. (2013). An SET Tolerant Tree Arbiter Cell. In Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on (p. 9). http://hdl.handle.net/20.500.12708/55001
- Muller C-Element Metastability Containment / Polzer, T., Steininger, A., & Lechner, J. (2013). Muller C-Element Metastability Containment. In Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (pp. 103–112). Lecture Notes in Computer Science. http://hdl.handle.net/20.500.12708/54509
- A Generic Architecture for Robust Asynchronous Communication Links / Lechner, J., & Najvirt, R. (2013). A Generic Architecture for Robust Asynchronous Communication Links. In Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (pp. 121–130). Lecture Notes in Computer Science. http://hdl.handle.net/20.500.12708/54501
- Protecting Pipelined Asynchronous Communication Channels Against Single Event Upsets / Lechner, J., & Lampacher, M. (2012). Protecting Pipelined Asynchronous Communication Channels Against Single Event Upsets. In Computer Design (ICCD), 2012 IEEE 30th International Conference on (pp. 480–481). http://hdl.handle.net/20.500.12708/54527
- A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding / Lechner, J., Lampacher, M., & Polzer, T. (2012). A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding. In Application of Concurrency to System Design (ACSD), 2012 12th International Conference on (pp. 122–131). http://hdl.handle.net/20.500.12708/54526
- Designing Robust GALS Circuits with Triple Modular Redundancy / Lechner, J. (2012). Designing Robust GALS Circuits with Triple Modular Redundancy. In Dependable Computing Conference (EDCC), 2012 Ninth European (pp. 227–236). http://hdl.handle.net/20.500.12708/54525
- Enhancing pipelined processor architectures with fast autonomous recovery of transient faults / Jeitler, M., Lechner, J., & Steininger, A. (2010). Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE Computer Society. https://doi.org/10.1109/ddecs.2010.5491776
- Low Latency Recovery from Transient Faults for Pipelined Processor Architectures / Jeitler, M., & Lechner, J. (2010). Low Latency Recovery from Transient Faults for Pipelined Processor Architectures. In 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. DSD 2010 (Euromicro Conference on Digital System Design), Lille, France, EU. IEEE Computer Society. https://doi.org/10.1109/dsd.2010.87
- Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation / Jeitler, M., & Lech, J. (2009). Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation. In 2009 International Conference on Reconfigurable Computing and FPGAs. ReConFig 2009 (International Conference on ReConFigurable Computing and FPGAs), Cancun, Quintana Roo, Mexico, Non-EU. CPS. https://doi.org/10.1109/reconfig.2009.35
- Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection / Jeitler, M., & Lechner, J. (2009). Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection. In MEMICS 2009 proceedings (pp. 110–117). Universität Brno. http://hdl.handle.net/20.500.12708/52876
- Implementation of a design tool for generation of FSL circuits / Lechner, J. (2008). Implementation of a design tool for generation of FSL circuits [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/182090
- Implementation of a Design Tool for Automated Generation of Four State Logic Circuits / Lechner, J., & Delvai, M. (2008). Implementation of a Design Tool for Automated Generation of Four State Logic Circuits. In Proceedings of the Junior Scientist Conference 2008 (pp. 85–86). http://hdl.handle.net/20.500.12708/52477
- Design Variety in Hardware/Software Codesign - Implementations of an AES Encoder / Ambrosch, K., Helpa, C., Lechner, J., Leidenfrost, R., Panhofer, T., platschek, A., Ramberger, S., Stadler, U., Steiner, D., Trinkl, H., Widtmann, C., & Delvai, M. (2006). Design Variety in Hardware/Software Codesign - Implementations of an AES Encoder. In Austrochip Mikroelektroniktagung (pp. 181–188). Austrochip 2006. http://hdl.handle.net/20.500.12708/51525
Supervisions
- Design and evaluation of an AXI4 bus system / Pados, K. D. (2013). Design and evaluation of an AXI4 bus system [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/159734