TU Wien Informatics

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Markus Ferringer

Univ.Lektor Dipl.-Ing. Dr.techn.

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  • Asynchronous logic in real-time systems / Ferringer, M. (2012). Asynchronous logic in real-time systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-46960
    Download: PDF (1.83 MB)
  • On Self-Timed Circuits in Real-Time Systems / Ferringer, M. (2011). On Self-Timed Circuits in Real-Time Systems. International Journal of Reconfigurable Computing, 2011, 1–16. https://doi.org/10.1155/2011/972375
    Project: ARTS (2007–2011)
  • Investigating the impact of process variations on an asynchronous Time-Triggered-Protocol controller / Ferringer, M. (2011). Investigating the impact of process variations on an asynchronous Time-Triggered-Protocol controller. In 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops (DSN-W). Dependable Systems and Networks Workshops (DSN-W), 2011 IEEE/IFIP 41st International Conference on, Hong-Kong, Non-EU. https://doi.org/10.1109/dsnw.2011.5958834
    Project: ARTS (2007–2011)
  • Conversion and interfacing techniques for asynchronous circuits / Ferringer, M. (2011). Conversion and interfacing techniques for asynchronous circuits. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011), Cottbus, Germany, EU. https://doi.org/10.1109/ddecs.2011.5783039
    Project: ARTS (2007–2011)
  • Conversion of two- to four-phase delay-insensitive asynchronous circuits / Ferringer, M. (2011). Conversion of two- to four-phase delay-insensitive asynchronous circuits. In 2011 IEEE EUROCON - International Conference on Computer as a Tool. EUROCON 2011, Lisbon, EU. https://doi.org/10.1109/eurocon.2011.5929318
    Project: ARTS (2007–2011)
  • Investigating Self-Timed Circuits for the Time-Triggered Protocol / Ferringer, M. (2010). Investigating Self-Timed Circuits for the Time-Triggered Protocol. In Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 (pp. 101–108). KIT Scientific Publishing - DFG. http://hdl.handle.net/20.500.12708/53494
    Project: ARTS (2007–2011)
  • Towards self-timed logic in the Time-Triggered Protocol / Ferringer, M. (2010). Towards self-timed logic in the Time-Triggered Protocol. In 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W). DSN 2010 (International Conference on Dependable Systems and Networks), Chicago, IL, USA, Non-EU. IEEE Computer Society. https://doi.org/10.1109/dsnw.2010.5542607
    Project: THETA (2004–2008)
  • Coupling Asynchronous Signals into Asynchronous Logic / Ferringer, M. (2009). Coupling Asynchronous Signals into Asynchronous Logic. In Austrochip (pp. 97–102). Institut für Elektronik - TU Graz. http://hdl.handle.net/20.500.12708/52854
    Project: ARTS (2007–2011)
  • An asynchronous hardware design for distributed tick generation / Ferringer, M. (2006). An asynchronous hardware design for distributed tick generation [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/179556
  • VLSI Implementation of a Fault-Tolerant Distributed Clock Generation / Ferringer, M., Fuchs, G., Steininger, A., & Kempf, G. (2006). VLSI Implementation of a Fault-Tolerant Distributed Clock Generation. In The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (pp. 563–571). http://hdl.handle.net/20.500.12708/51509
    Project: DARTS (2005–2010)