Daniel Müller-Gritschneder
Univ.Prof. Dr.-Ing. Dipl.-Ing.
Research Focus
- Computer Engineering: 100%
Research Areas
- Computer Engineering, Embedded Systems, Embedded System Design, Computer Architecture, RISC-V, computer security, Edge AI
About
I am full professor of Computer Architecture at the Institute of Computer Engineering, TU Wien Informatics, Austria, since 2024. Previously, I was a research group leader at the Chair of Electronic Design Automation and acting professor for Real-time Systems at TU Munich, Germany. I received my Dipl.-Ing., Dr.-Ing. and Habilitation degree from TUM in 2003, 2009 and 2019 respectively.
I like working in collaborative research projects in close cooperation with industry partners and in the past cooperated with companies such as Infineon, Bosch, SPARX Systems, BMW and Mercedes.
I often serve in committees fort EDA conferences such as DAC, ICCAD, DATE, SAMOS and CODES/ISSS. I am also active in the RISC-V community and co-initiator and steering committee member of the RISC-V Summit Europe. I am senior member of IEEE.
My main research interests are in Electronic System Level Design, RISC-V domain-specific architectures, tinyML/embedded ML compiler toolchains as well as functional safety and HW security.
Roles
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Full Professor
Embedded Computing Systems, E191-02 -
Curriculum Commission for Computer Engineering
Substitute Member
Courses
2024W
- Bachelor Thesis for Computer Science and Business Informatics / 182.698 / PR
- Computer Engineering Practical / 191.005 / PR
- Computer Engineering Project / 191.006 / PR
- Doctorand's seminar / 182.070 / SE
- High-Level Synthesis / 191.010 / VU
- Project in Computer Science 1 / 191.008 / PR
- Project in Computer Science 2 / 191.009 / PR
- Scientific Project Computer Engineering / 191.007 / PR
- Scientific Research and Writing / 193.052 / SE
- Seminar Computer Engineering / 182.757 / SE
2025S
- Bachelor Thesis for Computer Science and Business Informatics / 182.698 / PR
- Computer Engineering Practical / 191.005 / PR
- Computer Engineering Project / 191.006 / PR
- Computer Organization and Design / 182.690 / VO
- Computer Systems / 191.003 / VU
- Digital Design and Computer Architecture / 191.016 / LU
- Doctorand's seminar / 182.070 / SE
- Project in Computer Science 1 / 191.008 / PR
- Project in Computer Science 2 / 191.009 / PR
- Scientific Project Computer Engineering / 191.007 / PR
- Seminar Computer Engineering / 182.757 / SE
Projects
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Generating and Deploying Lightweight, Secure and Zero-overhead Software for Multipurpose IoT Devices
2025 – 2026 / XCoorp GmbH
Publications
- EGIC: Enhanced Low-Bit-Rate Generative Image Compression Guided by Semantic Segmentation / Körber, N., Kromer, E., Siebert, A., Hauke, S., Mueller-Gritschneder, D., & Schuller, B. (2025). EGIC: Enhanced Low-Bit-Rate Generative Image Compression Guided by Semantic Segmentation. In A. Leonardis, E. Ricci, & S. Roth (Eds.), Computer Vision – ECCV 2024 : 18th European Conference, Milan, Italy, September 29 – October 4, 2024, Proceedings, Part XXXV (pp. 202–220). Springer. https://doi.org/10.1007/978-3-031-72761-0_12
- Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization / van Kempen, P., Salmen, M., Müller-Gritschneder, D., & Schlichtmann, U. (2024). Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization. In Proceedings 2024 27th Euromicro Conference on Digital System Design (DSD 2024) (pp. 335–342). https://doi.org/10.1109/DSD64264.2024.00052
- Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions / Foik, C., Kunzelmann, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2024). Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43(11), 4130–4141. https://doi.org/10.1109/TCAD.2024.3445255
- Rapid Prototyping Methods for custom-tailored, safe and secure RISC-V processors / Müller-Gritschneder, D. (2024, September 11). Rapid Prototyping Methods for custom-tailored, safe and secure RISC-V processors [Conference Presentation]. TRISTAN Technical Conference 2024, Graz, Austria. http://hdl.handle.net/20.500.12708/206261
- Open Source Simulators for Pre-Silicon Validation of Safety-critical RISC-V System-on-chip / Mueller-Gritschneder, D., & Geier, J. (2024, September). Open Source Simulators for Pre-Silicon Validation of Safety-critical RISC-V System-on-chip [Conference Presentation]. Open Source Summit 2024, Wien, Austria. http://hdl.handle.net/20.500.12708/206489
- MuDSE: GA-ILP-based Framework for Automated Deployment of Multiple DNNs on Heterogeneous Mixed-Criticality Systems / Hoffman, A., Fnayou, A., Smirnov, F., Müller-Gritschneder, D., & Schlichtmann, U. (2024). MuDSE: GA-ILP-based Framework for Automated Deployment of Multiple DNNs on Heterogeneous Mixed-Criticality Systems. In 2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS). IEEE COINS 2024: IEEE International Conference on Omni-layer Intelligent systems, London, United Kingdom of Great Britain and Northern Ireland (the). IEEE. https://doi.org/10.1109/COINS61597.2024.10622135
Awards
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Best Student Paper Award: Pierpaolo Mori, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Moritz Thoma, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Christian Unger, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone "Wino Vidi Vici: Conquering Numerical Instability of 8-Bit Winograd Convolution for Accurate Inference Acceleration on Edge"
2024 / IEEE/CVF Winter Conference on Applications of Computer Vision 2024 / USA -
Best Paper Award: Samira Ahmadi, Rafael Stahl, Philipp van Kempen, Daniel Mueller-Gritschneder and Ulf Schlichtmann. "Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM’s UMA."
2023 / Workshop on Compilers, Deployment, and Tooling for Edge AI. / Germany -
Habilitationspreis
2019 / Bund der Freunde der technischen Universität München / Germany / Website -
Best Paper Award for Paper: Saman Payvar, Mir Khan, Rafael Stahl, Daniel Mueller-Gritschneder, Jani Boutellier "Neural Network-based Vehicle Image Classification for IoT Devices"
2019 / IEEE International Workshop on Signal Processing Systems, SiPS 2019 / China -
Senior Member
2019 / IEEE / USA
And more…
Soon, this page will include additional information such as reference projects, activities as journal reviewer and editor, memberships in councils and committees, and other research activities.
Until then, please visit Daniel Müller-Gritschneder’s research profile in TISS .