2024W

• Bachelor Thesis for Computer Science and Business Informatics / 182.698 / PR
• Computer Engineering Practical / 191.005 / PR
• Computer Engineering Project / 191.006 / PR
• Doctorand's seminar / 182.070 / SE
• High-Level Synthesis / 191.010 / VU
• Project in Computer Science 1 / 191.008 / PR
• Project in Computer Science 2 / 191.009 / PR
• Scientific Project Computer Engineering / 191.007 / PR
• Scientific Research and Writing / 193.052 / SE
• Seminar Computer Engineering / 182.757 / SE

2025S

• Computer Engineering Practical / 191.005 / PR
• Computer Engineering Project / 191.006 / PR
• Project in Computer Science 1 / 191.008 / PR
• Project in Computer Science 2 / 191.009 / PR
• Scientific Project Computer Engineering / 191.007 / PR

• EGIC: Enhanced Low-Bit-Rate Generative Image Compression Guided by Semantic Segmentation / Körber, N., Kromer, E., Siebert, A., Hauke, S., Mueller-Gritschneder, D., & Schuller, B. (2025). EGIC: Enhanced Low-Bit-Rate Generative Image Compression Guided by Semantic Segmentation. In A. Leonardis, E. Ricci, & S. Roth (Eds.), Computer Vision – ECCV 2024 : 18th European Conference, Milan, Italy, September 29 – October 4, 2024, Proceedings, Part XXXV (pp. 202–220). Springer. https://doi.org/10.1007/978-3-031-72761-0_12
• Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization / van Kempen, P., Salmen, M., Müller-Gritschneder, D., & Schlichtmann, U. (2024). Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization. In Proceedings 2024 27th Euromicro Conference on Digital System Design (DSD 2024) (pp. 335–342). https://doi.org/10.1109/DSD64264.2024.00052
• Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions / Foik, C., Kunzelmann, R., Mueller-Gritschneder, D., & Schlichtmann, U. (2024). Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43(11), 4130–4141. https://doi.org/10.1109/TCAD.2024.3445255
• Rapid Prototyping Methods for custom-tailored, safe and secure RISC-V processors / Müller-Gritschneder, D. (2024, September 11). Rapid Prototyping Methods for custom-tailored, safe and secure RISC-V processors [Conference Presentation]. TRISTAN Technical Conference 2024, Graz, Austria. http://hdl.handle.net/20.500.12708/206261
• Open Source Simulators for Pre-Silicon Validation of Safety-critical RISC-V System-on-chip / Mueller-Gritschneder, D., & Geier, J. (2024, September). Open Source Simulators for Pre-Silicon Validation of Safety-critical RISC-V System-on-chip [Conference Presentation]. Open Source Summit 2024, Wien, Austria.
• MuDSE: GA-ILP-based Framework for Automated Deployment of Multiple DNNs on Heterogeneous Mixed-Criticality Systems / Hoffman, A., Fnayou, A., Smirnov, F., Müller-Gritschneder, D., & Schlichtmann, U. (2024). MuDSE: GA-ILP-based Framework for Automated Deployment of Multiple DNNs on Heterogeneous Mixed-Criticality Systems. In 2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS). IEEE COINS 2024: IEEE International Conference on Omni-layer Intelligent systems, London, United Kingdom of Great Britain and Northern Ireland (the). IEEE. https://doi.org/10.1109/COINS61597.2024.10622135