2024W

• Advanced Digital Design / 182.754 / LU
• Advanced Digital Design / 182.755 / VU
• Bachelor Thesis for Computer Science and Business Informatics / 182.698 / PR
• Computer Engineering Practical / 191.005 / PR
• Computer Engineering Project / 191.006 / PR
• Hardware Modeling / 191.011 / VU
• HW/SW Codesign / 182.701 / LU
• Project in Computer Science 1 / 191.008 / PR
• Project in Computer Science 2 / 191.009 / PR
• Scientific Project Computer Engineering / 191.007 / PR
• Seminar Computer Engineering / 182.757 / SE

• Self-stabilizing Byzantine Fault-Tolerant Distributed Algorithms for Integrated Circiuts
  2013 – 2018 / Austrian Science Fund (FWF)
  Publication: 485

• Synchronizing Independent Ring Oscillators on an FPGA / Fiedler, C., Huemer, F., & Steininger, A. (2024). Synchronizing Independent Ring Oscillators on an FPGA. In 2024 Austrochip Workshop on Microelectronics (Austrochip) (pp. 1–4). https://doi.org/10.1109/Austrochip62761.2024.10716225
• QDI Binary Comparator Networks and their Application in Combinational Logic / Huemer, F. (2024). QDI Binary Comparator Networks and their Application in Combinational Logic. In 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS) (pp. 92–97). https://doi.org/10.1109/DDECS60919.2024.10508908
• ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic / Tabassam, Z., Steininger, A., Najvirt, R., & Huemer, F. (2023). ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. In 2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (pp. 48–57). IEEE. https://doi.org/10.1109/ASYNC58294.2023.10239589
• Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles / Behal, P., Huemer, F., Najvirt, R., Tabassam, Z., & Steininger, A. (2021). Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. In 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (pp. 25–33). IEEE. https://doi.org/10.34726/3945
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• An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits / Behal, P., Huemer, F. F., Najvirt, R., & Steininger, A. (2021). An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. In 2021 24th Euromicro Conference on Digital System Design (DSD). 24th Euromicro Conference on Digital System Design, Palermo, Italy, EU. https://doi.org/10.34726/4044
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• Sorting Network based Full Adders for QDI Circuits / Huemer, F. F., & Steininger, A. (2020). Sorting Network based Full Adders for QDI Circuits. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. https://doi.org/10.34726/4042
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• Identification and Confinement of Fault Sensitivity Windows in QDI Logic / Huemer, F. F., Najvirt, R., & Steininger, A. (2020). Identification and Confinement of Fault Sensitivity Windows in QDI Logic. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. https://doi.org/10.34726/4043
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• Timing Domain Crossing using Muller Pipelines / Huemer, F. F., & Steininger, A. (2020). Timing Domain Crossing using Muller Pipelines. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 26th IEEE International Symposium on Asynchronous Circuits and Systems, Snowbird, Utah, USA, Austria. Ieee Cs. https://doi.org/10.34726/4041
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• An Experimental Study of Metastability-Induced Glitching Behavior / Polzer, T., Huemer, F., & Steininger, A. (2019). An Experimental Study of Metastability-Induced Glitching Behavior. Journal of Circuits, Systems, and Computers, 28(supp01), 1940006. https://doi.org/10.1142/s0218126619400061
• Novel Approaches for Efficient Delay-Insensitive Communication / Huemer, F., & Steininger, A. (2019). Novel Approaches for Efficient Delay-Insensitive Communication. Journal of Low Power Electronics and Applications, 9(2), 16. https://doi.org/10.3390/jlpea9020016
• Refined Metastability Characterization Using a Time-to-Digital Converter / Polzer, T., Huemer, F., & Steininger, A. (2018). Refined Metastability Characterization Using a Time-to-Digital Converter. Microelectronics Reliability, 80, 91–99. https://doi.org/10.1016/j.microrel.2017.11.017
• Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA / Huemer, F., Polzer, T., & Steininger, A. (2018). Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. In 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/ddecs.2018.00032
• State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration / Schütz, M., Steininger, A., Huemer, F., & Lechner, J. (2018). State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/dft.2018.8602984
  Project: Intel CARS (2017–2019)
• Advanced Delay-Insensitive 4-Phase Protocols / Huemer, F., & Steininger, A. (2018). Advanced Delay-Insensitive 4-Phase Protocols. In 2018 Austrochip Workshop on Microelectronics (Austrochip). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/austrochip.2018.8520702
• Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication / Huemer, F., & Steininger, A. (2018). Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. In 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/async.2018.00014
• Protecting 4-phase delay-insensitive communication against transient faults / Huemer, F. F. (2017). Protecting 4-phase delay-insensitive communication against transient faults [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2017.30269
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• Measuring metastability using a time-to-digital converter / Polzer, T., Huemer, F., & Steininger, A. (2017). Measuring metastability using a time-to-digital converter. In 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Dresden, EU. IEEE Service Center. https://doi.org/10.1109/ddecs.2017.7934582
• Fault-Tolerant Clock Synchronization with High Precision / Kinali, A., Huemer, F., & Lenzen, C. (2016). Fault-Tolerant Clock Synchronization with High Precision. In 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2016 IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, USA, Non-EU. https://doi.org/10.1109/isvlsi.2016.88
• A Programmable Delay Line for Metastability Characterization in FPGAs / Polzer, T., Huemer, F., & Steininger, A. (2016). A Programmable Delay Line for Metastability Characterization in FPGAs. In Proceedings 24th Austrian Workshop on Microelectronics (p. 6). http://hdl.handle.net/20.500.12708/56883
• A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes / Huemer, F., Lechner, J., & Steininger, A. (2016). A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes. In Proceedings 2016 IEEE International Conference on Computer Design (pp. 392–395). http://hdl.handle.net/20.500.12708/56881
• Revisiting Sorting Network based Completion Detection for 4 Phase Delay Insensitive Codes / Huemer, F., Schütz, M., & Steininger, A. (2015). Revisiting Sorting Network based Completion Detection for 4 Phase Delay Insensitive Codes. In Austrochip Workshop on Microelectronics (p. 6). http://hdl.handle.net/20.500.12708/56350
• A Practical Comparison of 2-Phase Delay Insensitve Communication Protocols / Schütz, M., Huemer, F., & Steininger, A. (2015). A Practical Comparison of 2-Phase Delay Insensitve Communication Protocols. In Austrochip Workshop on Microelectronics (p. 6). http://hdl.handle.net/20.500.12708/56349
• Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes / Lechner, J., Steininger, A., & Huemer, F. (2015). Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes. In 33rd IEEE International Conference on Computer Design (p. 8). http://hdl.handle.net/20.500.12708/56358

• Comparison of QDI adders / Haschke, O. (2024). Comparison of QDI adders [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2024.107664
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• Implementation of an automated fault-injection framework for QDI circuits / Spitzer, J. (2024). Implementation of an automated fault-injection framework for QDI circuits [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2024.107665
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• Evaluation of different tools for design and fault-injection of asynchronous circuits / Schwendinger, M. (2022). Evaluation of different tools for design and fault-injection of asynchronous circuits [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2022.98624
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• Smart SoC testing and remote configuration facilitated by the use of IJTAG complemented with on-chip microprocessor access / Pircher, C. (2022). Smart SoC testing and remote configuration facilitated by the use of IJTAG complemented with on-chip microprocessor access [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2022.98141
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• Quantitative Comparison of the sensitivity of delay-insensitive design templates to transient faults / Behal, P. (2021). Quantitative Comparison of the sensitivity of delay-insensitive design templates to transient faults [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2021.81601
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