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Andreas Steininger

Ao.Univ.Prof. Dipl.-Ing. Dr.techn.

Research Focus

  • Computer Engineering: 100%

Research Areas

  • Timing domain interfacing, Clockless Processors, Dependable Computer Systems, Error Detection Mechanisms, Fault Tolerance, Computer Architecture, Built in Self Test (BIST)
Andreas Steininger

About

Asynchronous Logic, Fault Tolerant Clocking, Timing Domain Interfacing (Metastability), Fault Tolerant Architectures, Radiation Effects in Micorelectronics, Fault Injection, trustworthy systems, sustainable computing, computer engineering

Roles

  • Associate Professor
    Embedded Computing Systems, E191-02
  • Doctoral School
    Director
  • Curriculum Commission for Computer Engineering
    Principal Member

Contact

2024W

2025S

 

2024

2023

2022

  • ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons / Prabakaran, B. S., Fasching, F., Schreib, J., Steininger, A., & Shafique, M. (2022). ATLAS: An IoT Architecture and Secure Open-source Networking Stack for Anonymous Localization and Tracking Using Smartphones and Bluetooth Beacons. arXiv. https://doi.org/10.34726/3642
    Download: PDF (2.02 MB)
  • Study and Comparison of QDI Pipeline Components' Sensitivity to Permanent Faults / Elshehaby, R., & Steininger, A. (2022). Study and Comparison of QDI Pipeline Components’ Sensitivity to Permanent Faults. In 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Austin, TX, United States of America (the). IEEE. https://doi.org/10.34726/4047
    Download: PDF (381 KB)
  • SET Hardened Derivatives of QDI Buffer Template / Tabassam, Z., & Steininger, A. (2022). SET Hardened Derivatives of QDI Buffer Template. In 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Austin, TX, United States of America (the). IEEE. https://doi.org/10.34726/3944
    Download: PDF (467 KB)
  • Towards Resilient QDI Pipeline Implementations / Tabassam, Z., & Steininger, A. (2022). Towards Resilient QDI Pipeline Implementations. In 2022 25th Euromicro Conference on Digital System Design (DSD) (pp. 657–664). IEEE. https://doi.org/10.34726/3942
    Download: PDF (597 KB)
  • AμFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages / Tabassam, Z., Naqvi, S. R., & Steininger, A. (2022). AμFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (pp. 32–37). IEEE. https://doi.org/10.34726/3941
    Download: PDF (435 KB)
  • enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks / Colucci, A., Steininger, A., & Shafique, M. (2022). enpheeph: A Fault Injection Framework for Spiking and Compressed Deep Neural Networks. In Proceedings 2022 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS) (pp. 5155–5162). https://doi.org/10.1109/IROS47612.2022.9982181

2021

2020

  • Sorting Network based Full Adders for QDI Circuits / Huemer, F. F., & Steininger, A. (2020). Sorting Network based Full Adders for QDI Circuits. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. https://doi.org/10.34726/4042
    Download: PDF (280 KB)
  • Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock / Duer, W., & Steininger, A. (2020). Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock. In 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Novi Sad, Serbia. Ieee Cs. https://doi.org/10.1109/ddecs50862.2020.9095577
  • Identification and Confinement of Fault Sensitivity Windows in QDI Logic / Huemer, F. F., Najvirt, R., & Steininger, A. (2020). Identification and Confinement of Fault Sensitivity Windows in QDI Logic. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. https://doi.org/10.34726/4043
    Download: PDF (1.76 MB)
  • Timing Domain Crossing using Muller Pipelines / Huemer, F. F., & Steininger, A. (2020). Timing Domain Crossing using Muller Pipelines. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 26th IEEE International Symposium on Asynchronous Circuits and Systems, Snowbird, Utah, USA, Austria. Ieee Cs. https://doi.org/10.34726/4041
    Download: PDF (330 KB)
  • On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective / Elshehaby, R., & Steininger, A. (2020). On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. In 2020 IEEE 38th International Conference on Computer Design (ICCD). IEEE International Conference on Computer Design, Hartford, Connecticut, USA, Austria. https://doi.org/10.34726/4045
    Download: PDF (462 KB)
  • Welcome Message: ASYNC 2020 / Brunvand, E., Stevens, K., Moreira, M., & Steininger, A. (2020). Welcome Message: ASYNC 2020. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE Computer Society. https://doi.org/10.1109/async49171.2020.00005

2019

  • A Systematic Approach to Clock Failure Detection / Steininger, A., & Schwendinger, M. (2019). A Systematic Approach to Clock Failure Detection. In 2019 Austrochip Workshop on Microelectronics (Austrochip). Austrochip Workshop on Microelectronics, Wien, Austria. https://doi.org/10.1109/austrochip.2019.00018
    Project: Intel CARS (2017–2019)
  • Efficient Metastability Characterization for Schmitt-Triggers / Maier, J., & Steininger, A. (2019). Efficient Metastability Characterization for Schmitt-Triggers. In 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 25th IEEE International Symposium on Asynchronous Circuits and Systems, Hirosaki, Japan. https://doi.org/10.1109/ASYNC.2019.00024
    Download: PDF (799 KB)
  • Sustainable Security & Safety: Challenges and Opportunities / Paverd, A., Völp, M., Brasser, F., Schunter, M., Asokan, N., Sadeghi, A.-R., Esteves-Verissimo, P., Steininger, A., & Holz, T. (2019). Sustainable Security & Safety: Challenges and Opportunities. In M. Asplund & M. Paulitsch (Eds.), Proceedings 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems (CERTS 2019) (p. 13). Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/OASIcs.CERTS.2019.4
    Project: Intel CARS (2017–2019)
  • An Experimental Study of Metastability-Induced Glitching Behavior / Polzer, T., Huemer, F., & Steininger, A. (2019). An Experimental Study of Metastability-Induced Glitching Behavior. Journal of Circuits, Systems, and Computers, 28(supp01), 1940006. https://doi.org/10.1142/s0218126619400061
  • Special Issue "Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018" / Krstic, M., Jones, I., Steininger, A., & Függer, M. (2019). Special Issue “Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018.” Journal of Low Power Electronics and Applications, 9(2), 2. http://hdl.handle.net/20.500.12708/143834
  • Novel Approaches for Efficient Delay-Insensitive Communication / Huemer, F., & Steininger, A. (2019). Novel Approaches for Efficient Delay-Insensitive Communication. Journal of Low Power Electronics and Applications, 9(2), 16. https://doi.org/10.3390/jlpea9020016

2018

  • Refined Metastability Characterization Using a Time-to-Digital Converter / Polzer, T., Huemer, F., & Steininger, A. (2018). Refined Metastability Characterization Using a Time-to-Digital Converter. Microelectronics Reliability, 80, 91–99. https://doi.org/10.1016/j.microrel.2017.11.017
  • Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA / Huemer, F., Polzer, T., & Steininger, A. (2018). Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. In 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/ddecs.2018.00032
  • State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration / Schütz, M., Steininger, A., Huemer, F., & Lechner, J. (2018). State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/dft.2018.8602984
    Project: Intel CARS (2017–2019)
  • Advanced Delay-Insensitive 4-Phase Protocols / Huemer, F., & Steininger, A. (2018). Advanced Delay-Insensitive 4-Phase Protocols. In 2018 Austrochip Workshop on Microelectronics (Austrochip). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/austrochip.2018.8520702
  • Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication / Huemer, F., & Steininger, A. (2018). Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. In 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/async.2018.00014

2017

  • Foreword / Steininger, A., Pawlak, A., & Stopjakova, V. (2017). Foreword. Journal of Circuits, Systems, and Computers, 26(08), Article 1702001. https://doi.org/10.1142/s0218126617020017
  • A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study / Andjelkovic, M., Krstic, M., Kraemer, R., Veeravalli, V. S., & Steininger, A. (2017). A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. In Proceedings of the 26th IEEE Asian Test Symposium (ATS´17) (pp. 1–6). http://hdl.handle.net/20.500.12708/57265
  • Measuring Metastability with Free-Running Clocks / Najvirt, R., Polzer, T., & Steininger, A. (2017). Measuring Metastability with Free-Running Clocks. In 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California, United States of America (the). IEEE Computer Society. https://doi.org/10.1109/async.2017.18
  • Measuring metastability using a time-to-digital converter / Polzer, T., Huemer, F., & Steininger, A. (2017). Measuring metastability using a time-to-digital converter. In 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Dresden, Germany. IEEE Service Center. https://doi.org/10.1109/ddecs.2017.7934582
  • Setup for an Experimental Study of Radiation Effects in 65nm CMOS / Fritz, B., Veeravalli, V. S., Steininger, A., & Simek, V. (2017). Setup for an Experimental Study of Radiation Effects in 65nm CMOS. In 2017 Euromicro Conference on Digital System Design (DSD). 20th Euromicro Conference on Digital System Design, Wien, Austria. https://doi.org/10.1109/dsd.2017.60
  • A Model for the Metastability Delay of Sequential Elements / Polzer, T., & Steininger, A. (2017). A Model for the Metastability Delay of Sequential Elements. Journal of Circuits, Systems, and Computers, 26(08), 1740010. https://doi.org/10.1142/s0218126617400102
  • A versatile architecture for long-term monitoring of single-event transient durations / Savulimedu Veeravalli, V., Steininger, A., & Schmid, U. (2017). A versatile architecture for long-term monitoring of single-event transient durations. Microprocessors and Microsystems, 53, 130–144. https://doi.org/10.1016/j.micpro.2017.07.007

2016

  • A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes / Huemer, F., Lechner, J., & Steininger, A. (2016). A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes. In Proceedings 2016 IEEE International Conference on Computer Design (pp. 392–395). http://hdl.handle.net/20.500.12708/56881
  • A General Approach for Comparing Metastable Behavior of Digital CMOS Gates / Polzer, T., & Steininger, A. (2016). A General Approach for Comparing Metastable Behavior of Digital CMOS Gates. In Proc 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (p. 6). http://hdl.handle.net/20.500.12708/56886
  • Study of a Delayed Single-Event Effect in the Muller C-element / Veeravalli, V. S., & Steininger, A. (2016). Study of a Delayed Single-Event Effect in the Muller C-element. In Proc 21st IEEE European Test Symposium. 21st IEEE European Test Symposium, Amsterdam, Netherlands (the). http://hdl.handle.net/20.500.12708/56885
    Project: EASET (2014–2017)
  • Design and Physical Implementation of a Target ASIC for SET Experiments / Veeravalli, V. S., & Steininger, A. (2016). Design and Physical Implementation of a Target ASIC for SET Experiments. In Proc. 2016 Euromicro Conference on Digital System Design (DSD) (pp. 694–697). IEEE. http://hdl.handle.net/20.500.12708/56884
    Project: EASET (2014–2017)
  • The Metastable Behavior of a Schmitt-Trigger / Steininger, A., Maier, J., & Najvirt, R. (2016). The Metastable Behavior of a Schmitt-Trigger. In 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), Porto Alegre, Brazil. IEEE. https://doi.org/10.1109/ASYNC.2016.19
    Download: PDF (503 KB)
  • Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? / Steininger, A., Najvirt, R., & Maier, J. (2016). Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? In 2016 Euromicro Conference on Digital System Design (DSD). 2016 Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus. IEEE. https://doi.org/10.1109/DSD.2016.56
    Download: PDF (347 KB)
  • Fifty Shades of Synchrony / Steininger, A. (2016). Fifty Shades of Synchrony. In A. Mokhov (Ed.), This Asynchronous Woirld (pp. 294–300). Newcastle University. http://hdl.handle.net/20.500.12708/29323
  • A Programmable Delay Line for Metastability Characterization in FPGAs / Polzer, T., Huemer, F., & Steininger, A. (2016). A Programmable Delay Line for Metastability Characterization in FPGAs. In Proceedings 24th Austrian Workshop on Microelectronics (p. 6). http://hdl.handle.net/20.500.12708/56883

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2011

  • Replicated processors on a single die - How independently do they fail? / Steininger, A., & Tummeltshammer, P. (2011). Replicated processors on a single die - How independently do they fail? Elektrotechnik Und Informationstechnik : E & i, 128(6), 245–250. https://doi.org/10.1007/s00502-011-0005-9
  • Automated test-trace inspection for microcontroller binary code / Reinbacher, T., Brauer, J., Schachinger, D., Steininger, A., & Kowalewski, S. (2011). Automated test-trace inspection for microcontroller binary code. In Runtime Verification (pp. 239–244). http://hdl.handle.net/20.500.12708/54078
    Project: CEVTES (2010–2013)
  • VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation / Fuchs, G., & Steininger, A. (2011). VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation. Journal of Electrical and Computer Engineering, 2011. https://doi.org/10.1155/2011/936712
    Project: DARTS (2005–2010)
  • Hardware support for efficient testing of embedded software / Reinbacher, T., Steininger, A., Müller, T., Horauer, M., Brauer, J., & Kowalewski, S. (2011). Hardware support for efficient testing of embedded software. In International Conference on Mechatronic and Embedded Systems and Applications. The 7th ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications, Washington, Non-EU. ASME. http://hdl.handle.net/20.500.12708/54082
    Project: CEVTES (2010–2013)
  • Past Time LTL Runtime Verification for Microcontroller Binary Code / Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., & Kowalewski, S. (2011). Past Time LTL Runtime Verification for Microcontroller Binary Code. In Formal Methods for Industrial Critical Systems (pp. 37–51). Springer Berlin / Heidelberg. https://doi.org/10.1007/978-3-642-24431-5_5
    Project: CEVTES (2010–2013)

2010

  • Test-Case Generation for Embedded Binary Code Using Abstract Interpretation / Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., & Kowalewski, S. (2010). Test-Case Generation for Embedded Binary Code Using Abstract Interpretation. In MEMICS proceedings (pp. 151–158). http://hdl.handle.net/20.500.12708/53554
    Project: CEVTES (2010–2013)
  • Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study. In 2010 NASA/ESA Conference on Adaptive Hardware and Systems. NASA/ESA 2010 (Conference on Adaptive Hardware and Systems), Anaheim, CA, USA, Non-EU. IEEE Computer Society. https://doi.org/10.1109/ahs.2010.5546277
  • Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm. In 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W). WSDN 2010 (4th Workshop on Dependable and Secure Nanocomputing, Chicago, IL, USA, Non-EU. IEEE Computer Socitey. https://doi.org/10.1109/dsnw.2010.5542609
  • A deterministic approach for hardware fault injection in asynchronous QDI logic / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). A deterministic approach for hardware fault injection in asynchronous QDI logic. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE. https://doi.org/10.1109/ddecs.2010.5491758
  • Enhancing pipelined processor architectures with fast autonomous recovery of transient faults / Jeitler, M., Lechner, J., & Steininger, A. (2010). Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE Computer Society. https://doi.org/10.1109/ddecs.2010.5491776

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