TU Wien Informatics

Overview Professors Scientific Staff Administrative Staff Student Staff External Lecturers By Responsibilities By Committee By Name
Related
Guest Professors Honoraries Alumni (LinkedIn) #5qw

Andreas Steininger

Ao.Univ.Prof. Dipl.-Ing. Dr.techn.

Research Focus

  • Computer Engineering: 100%

Research Areas

  • Timing domain interfacing, Clockless Processors, Dependable Computer Systems, Error Detection Mechanisms, Fault Tolerance, Computer Architecture, Built in Self Test (BIST)
Andreas Steininger

About

Asynchronous Logic, Fault Tolerant Clocking, Timing Domain Interfacing (Metastability), Fault Tolerant Architectures, Radiation Effects in Micorelectronics

Roles

Contact

2022W

2023S

 

Note: Due to the rollout of TU Wien’s new publication database, the list below may be slightly outdated. Once the migration is complete, everything will be up to date again.

2022

2021

  • Generation of a fault-tolerant clock through redundant crystal oscillators / Dür, W., Függer, M., & Steininger, A. (2021). Generation of a fault-tolerant clock through redundant crystal oscillators. Microelectronics Reliability, 120, 1–11. https://doi.org/10.1016/j.microrel.2021.114088
  • Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles / Behal, P., Huemer, F., Najvirt, R., Steininger, A., & Tabassam, Z. (2021). Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). https://doi.org/10.1109/async48570.2021.00012
  • Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses / Maier, J., Hartl-Nesic, C., & Steininger, A. (2021). Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(3), 1013–1026. https://doi.org/10.1109/tcsi.2021.3130349
  • Generation of a fault-tolerant clock through redundant crystal oscillators / Dür, W., Függer, M., & Steininger, A. (2021). Generation of a fault-tolerant clock through redundant crystal oscillators. Microelectronics Reliability, 120(114088), 114088. https://doi.org/10.1016/j.microrel.2021.114088
  • Foreword / Sekanina, L., Shafique, M., Krstic, M., Steininger, A., & Stojanovic, G. (2021). Foreword. In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE. https://doi.org/10.1109/ddecs52668.2021.9417019
  • An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits / Behal, P., Huemer, F., Najvirt, R., & Steininger, A. (2021). An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. In 2021 24th Euromicro Conference on Digital System Design (DSD). 24th Euromicro Conference on Digital System Design, Palermo, Italy, EU. https://doi.org/10.1109/dsd53832.2021.00087
  • Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles / Behal, P., Huemer, F., Najvirt, R., Tabassam, Z., & Steininger, A. (2021). Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. In 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 27th IEEE International Symposium on Asynchronous Circuits and Systems, online, Non-EU. https://doi.org/10.1109/async48570.2021.00012
  • Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines / El Shahaby, R., & Steininger, A. (2021). Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Wien, Austria. Ieee Cs. https://doi.org/10.1109/ddecs52668.2021.9417024
  • Input/Output-Interlocking for Fault Mitigation in QDI Pipelines / Tabassam, Z., Behal, P., Najvirt, R., & Steininger, A. (2021). Input/Output-Interlocking for Fault Mitigation in QDI Pipelines. In 2021 Austrochip Workshop on Microelectronics (Austrochip). 29th Austrian Workshop on Microelectronics, Linz, Austria. https://doi.org/10.1109/austrochip53290.2021.9576871

2020

  • Welcome Message: ASYNC 2020 / Brunvand, E., Stevens, K., Moreira, M., & Steininger, A. (2020). Welcome Message: ASYNC 2020. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE Computer Society. https://doi.org/10.1109/async49171.2020.00005
  • Identification and Confinement of Fault Sensitivity Windows in QDI Logic / Huemer, F., Najvirt, R., & Steininger, A. (2020). Identification and Confinement of Fault Sensitivity Windows in QDI Logic. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. https://doi.org/10.1109/austrochip51129.2020.9232985
  • Sorting Network based Full Adders for QDI Circuits / Huemer, F., & Steininger, A. (2020). Sorting Network based Full Adders for QDI Circuits. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. https://doi.org/10.1109/austrochip51129.2020.9232987
  • Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock / Duer, W., & Steininger, A. (2020). Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock. In 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Novi Sad, EU. Ieee Cs. https://doi.org/10.1109/ddecs50862.2020.9095577
  • On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective / El Shahaby, R., & Steininger, A. (2020). On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. In 2020 IEEE 38th International Conference on Computer Design (ICCD). IEEE International Conference on Computer Design, Hartford, Connecticut, USA, Non-EU. https://doi.org/10.1109/iccd50377.2020.00080
  • Timing Domain Crossing using Muller Pipelines / Huemer, F., & Steininger, A. (2020). Timing Domain Crossing using Muller Pipelines. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 26th IEEE International Symposium on Asynchronous Circuits and Systems, Snowbird, Utah, USA, Non-EU. Ieee Cs. https://doi.org/10.1109/async49171.2020.00014

2019

2018

2017

  • A Model for the Metastability Delay of Sequential Elements / Polzer, T., & Steininger, A. (2017). A Model for the Metastability Delay of Sequential Elements. Journal of Circuits, Systems, and Computers, 26(08), 1740010. https://doi.org/10.1142/s0218126617400102
  • A versatile architecture for long-term monitoring of single-event transient durations / Savulimedu Veeravalli, V., Steininger, A., & Schmid, U. (2017). A versatile architecture for long-term monitoring of single-event transient durations. Microprocessors and Microsystems, 53, 130–144. https://doi.org/10.1016/j.micpro.2017.07.007
  • Novel Trends in Design & Test / Steininger, A., Pawlak, A., & Stopjakova, V. (2017). Novel Trends in Design & Test. Journal of Circuits, Systems, and Computers, 26(08), 1702001. https://doi.org/10.1142/s0218126617020017
  • Setup for an Experimental Study of Radiation Effects in 65nm CMOS / Fritz, B., Veeravalli, V. S., Steininger, A., & Simek, V. (2017). Setup for an Experimental Study of Radiation Effects in 65nm CMOS. In 2017 Euromicro Conference on Digital System Design (DSD). 20th Euromicro Conference on Digital System Design, Wien, Austria. https://doi.org/10.1109/dsd.2017.60
  • A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study / Andjelkovic, M., Krstic, M., Kraemer, R., Veeravalli, V. S., & Steininger, A. (2017). A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. In Proceedings of the 26th IEEE Asian Test Symposium (ATS´17) (pp. 1–6). http://hdl.handle.net/20.500.12708/57265
  • Measuring metastability using a time-to-digital converter / Polzer, T., Huemer, F., & Steininger, A. (2017). Measuring metastability using a time-to-digital converter. In 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Dresden, EU. IEEE Service Center. https://doi.org/10.1109/ddecs.2017.7934582
  • Measuring Metastability with Free-Running Clocks / Najvirt, R., Polzer, T., & Steininger, A. (2017). Measuring Metastability with Free-Running Clocks. In 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California, Non-EU. IEEE Computer Society. https://doi.org/10.1109/async.2017.18

2016

2015

2014

2013

2012

2011

2010

  • Test-Case Generation for Embedded Binary Code Using Abstract Interpretation / Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., & Kowalewski, S. (2010). Test-Case Generation for Embedded Binary Code Using Abstract Interpretation. In MEMICS proceedings (pp. 151–158). http://hdl.handle.net/20.500.12708/53554 / Project: CEVTES
  • Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study. In 2010 NASA/ESA Conference on Adaptive Hardware and Systems. NASA/ESA 2010 (Conference on Adaptive Hardware and Systems), Anaheim, CA, USA, Non-EU. IEEE Computer Society. https://doi.org/10.1109/ahs.2010.5546277
  • Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm. In 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W). WSDN 2010 (4th Workshop on Dependable and Secure Nanocomputing, Chicago, IL, USA, Non-EU. IEEE Computer Socitey. https://doi.org/10.1109/dsnw.2010.5542609
  • A deterministic approach for hardware fault injection in asynchronous QDI logic / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). A deterministic approach for hardware fault injection in asynchronous QDI logic. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE. https://doi.org/10.1109/ddecs.2010.5491758
  • Enhancing pipelined processor architectures with fast autonomous recovery of transient faults / Jeitler, M., Lechner, J., & Steininger, A. (2010). Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE Computer Society. https://doi.org/10.1109/ddecs.2010.5491776

2009

2008

2007

2006

2005

2004

2003

 

Note: Due to the rollout of TU Wien’s new publication database, the list below may be slightly outdated. Once the migration is complete, everything will be up to date again.

2022

2021

2019

2018

2017

2016

2014

2013

2012

2011

2010

2009

2008

2006

2005

2004

2003