2021W

• Advanced Digital Design / 182.754 / LU
• Advanced Digital Design / 182.755 / VU
• Bachelor Thesis for Computer Science and Business Informatics / 182.698 / PR
• Computer Engineering Practical / 182.699 / PR
• Computer Engineering Project / 182.758 / PR
• Current Trends in Computer Science / 195.072 / VU
• Digital Design / 182.693 / VO
• Doctorand's seminar / 182.070 / SE
• HW/SW Codesign / 182.701 / LU
• HW/SW Codesign / 182.700 / VU
• Orientation Bachelor with Honors of Informatics and Business Informatics / 180.767 / SE
• Philosophy of Science / 195.080 / VU
• Propädeutikum für Informatik / 180.771 / VU
• Scientific Project Computer Engineering / 182.759 / PR
• Scientific Research and Writing / 193.052 / SE
• Seminar Computer Engineering / 182.757 / SE
• Seminar for Master Students in Computer Engineering / 180.778 / SE
• Strategic policy and technology challenges in the digital world, with a focus on the European Union / 199.095 / VU

2022S

• AI Policies: The Evolving Legal Domain / 199.101 / VU
• Bachelor Thesis for Computer Science and Business Informatics / 182.698 / PR
• Computer Engineering Practical / 182.699 / PR
• Computer Engineering Project / 182.758 / PR
• Current Trends in Computer Science / 195.072 / VU
• Defeasible Reasoning / 199.094 / VU
• Design of Asynchronous Circuits and Systems / 199.097 / VU
• Design-for-Trust in VLSI Circuits / 199.098 / VU
• Digital Design and Computer Architecture / 182.695 / LU
• Doctorand's seminar / 182.070 / SE
• Fundamental research methods for doctoral students / 195.079 / VU
• Orientation Bachelor with Honors of Informatics and Business Informatics / 180.767 / SE
• ProWriting -- Effective Research Project Proposal Writing for Public Funding / 195.109 / VU
• Scientific Project Computer Engineering / 182.759 / PR
• Seminar Computer Engineering / 182.757 / SE
• Seminar for Master Students in Computer Engineering / 180.778 / SE
• Software Design for Cyber-Physical Systems / 199.099 / VU
• Software Testing: From Basic Concepts to Advanced Topics / 199.102 / VU
• Verification of Probabilistic Programs / 199.100 / VU

 

• Robust Atomic Computing Platform and Enhanced Fault-Tolerant Distributed Algorithms 2
  2019 – 2022 / Intel Corporation
• Robust Atomic Computing Platform and Enhanced Fault-Tolerant Distributed Algorithms
  2017 – 2019 / Intel Corporation
• Analysis & Modeling of Single-Event-Transients in VLSI Chips
  2014 – 2017 / Austrian Science Fund (FWF)
• Self-stabilizing Byzantine Fault-Tolerant Distributed Algorithms for Integrated Circiuts
  2013 – 2018 / Austrian Science Fund (FWF)
• Configurable Data Prcessing Platform
  2013 – 2014 / Austrian Research Promotion Agency (FFG)
• Fehleranalyse MMU
  2012 / Robert Bosch GmbH
• CounterExample Validation and Test Case Generation Framework for Verifiying Embedded Software
  2010 – 2013 / Austrian Research Promotion Agency (FFG)
• Asynchronous Logic in Real-Time Systems
  2007 – 2011 / Austrian Research Promotion Agency (FFG)
• Distributed Algorithms for Robust Tick Synchronization
  2005 – 2010 / Austrian Research Promotion Agency (FFG)
• Exploiting Synchrony for Transparent Communication Services Testing
  2005 – 2008 / Austrian Research Promotion Agency (FFG)
• Systematic Test of Embedded Automotive Communication Systems
  2003 – 2008 / Austrian Research Promotion Agency (FFG)

2021

• Input/Output-Interlocking for Fault Mitigation in QDI Pipelines / Z. Tabassam, P. Behal, R. Najvirt, A. Steininger / Talk: 29th Austrian Workshop on Microelectronics, Linz; 2021-10-14; in: "Proceedings 29th Austrian Workshop on Microelectronics", (2021), ISBN: 978-1-6654-3661-8; 4 pages
• Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles / P. Behal, F. Huemer, R. Najvirt, Z. Tabassam, A. Steininger / Talk: 27th IEEE International Symposium on Asynchronous Circuits and Systems, online; 2021-09-07 - 2021-09-10; in: "Proceedings 27th IEEE International Symposium on Asynchronous Circuits and Systems", (2021), 1 - 8
• An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits / P. Behal, F. Huemer, R. Najvirt, A. Steininger / Talk: 24th Euromicro Conference on Digital System Design, Palermo, Italy; 2021-09-01 - 2021-09-03; in: "Proceedings of the 24th Euromicro Conference on Digital System Design", (2021), 1 - 8
• Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines / R. El Shahaby, A. Steininger / Talk: 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Wien; 2021-04-07 - 2021-04-09; in: "Proceedings 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", Ieee Cs, (2021), ISBN: 978-1-6654-3595-6; 1 - 6
• Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses / J. Maier, C. Hartl-Nesic, A. Steininger / IEEE Transactions on Circuits and Systems-I: Regular Papers, Dec (2021), 1 - 14
• Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles / P. Behal, F. Huemer, R. Najvirt, A. Steininger, Z. Tabassam / TCVLSI Newsletter (invited), 7 (2021), 4; 1 pages
• Generation of a fault-tolerant clock through redundant crystal oscillators / W. Dür, M. Függer, A. Steininger / Microelectronics Reliability, 120 (2021), 11 pages
• Foreword / L. Sekanina, M. Shafique, M. Krstic, A. Steininger, G. Stojanovic / in: "Proceedings 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", IEEE, 2021, (invited), ISBN: 978-1-6654-3595-6, 1 pages

2020

• On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective / R. El Shahaby, A. Steininger / Talk: IEEE International Conference on Computer Design, Hartford, Connecticut, USA; 2020-10-18 - 2020-10-21; in: "Proceedings IEEE International Conference on Computer Design", (2020), 1 - 4
• Sorting Network based Full Adders for QDI Circuits / F. Huemer, A. Steininger / Talk: 28th Austrian Workshop on Microelectronics, Wien; 2020-10-07; in: "Proceedings 28th Austrian Workshop on Microelectronics", (2020), 1 - 8
• Identification and Confinement of Fault Sensitivity Windows in QDI Logic / F. Huemer, R. Najvirt, A. Steininger / Talk: 28th Austrian Workshop on Microelectronics, Wien; 2020-10-07; in: "Proceedings 28th Austrian Workshop on Microelectronics", (2020), 1 - 8
• Timing Domain Crossing using Muller Pipelines / F. Huemer, A. Steininger / Talk: 26th IEEE International Symposium on Asynchronous Circuits and Systems, Snowbird, Utah, USA; 2020-05-17 - 2020-05-20; in: "Proceedings 26th IEEE International Symposium on Asynchronous Circuits and Systems", Ieee Cs, (2020), ISSN: 2643-1483; 1 - 10
• Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock / W. Dür, A. Steininger / Talk: 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Novi Sad; 2020-04-22 - 2020-04-24; in: "Proceedings 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", Ieee Cs, (2020), 1 - 6
• Welcome Message: ASYNC 2020 / E. Brunvand, K. Stevens, M. Moreira, A. Steininger / in: "Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)", IEEE Computer Society, 2020, (invited), ISBN: 978-1-7281-5495-4, 2 pages

2019

• A Systematic Approach to Clock Failure Detection / A. Steininger, M. Schwendinger / Talk: Austrochip Workshop on Microelectronics, Wien; 2019-10-24; in: "2019 Austrochip Workshop on Microelectronics (Austrochip)", (2019), ISBN: 978-1-7281-1953-3; 35 - 42
• Sustainable Security & Safety: Challenges andOpportunities / A. Paverd, M. Völp, F. Brasser, M. Schunter, N. Asokan, A. Sadeghi, P. Esteves-Verissimo, A. Steininger, T. Holz / Talk: 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems (CERTS 2019), Stuttgart; 2019-07-09; in: "Proceedings 4th International Workshop on Security and Dependability of Critical Embedded Real-Time Systems (CERTS 2019)", (2019), ISBN: 978-3-95977-119-1; 13 pages
• Efficient Metastability Characterization for Schmitt-Triggers / J. Maier, A. Steininger / Talk: 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), Hirosaki, Japan; 2019-05-12 - 2019-05-15; in: "2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)", (2019), ISBN: 978-1-5386-4747-9; 124 - 133
• An Experimental Study of Metastability-Induced Glitching Behavior / T. Polzer, F. Huemer, A. Steininger / Journal of Circuits, Systems, and Computers, 28 (2019), Suppl 1; 21 pages
• Novel Approaches for Efficient Delay-Insensitive Communication / F. Huemer, A. Steininger / Journal of Low Power Electronics and Applications, 9 (2019), 16; 41 pages
• Special Issue "Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018" / M. Krstic, I. Jones, A. Steininger, M Függer / Journal of Low Power Electronics and Applications, 9 (2019), 2; 2 pages

2018

• Refined Metastability Characterization Using a Time-to-Digital Converter / T. Polzer, F. Huemer, A. Steininger / Microelectronics Reliability, 80 (2018), 91 - 99
• Advanced Delay-Insensitive 4-Phase Protocols / F. Huemer, A. Steininger / in: "2018 Austrochip Workshop on Microelectronics (Austrochip)", issued by: IEEE CS Press; IEEE Xplore Digital Library, 2018, ISBN: 978-1-5386-8200-5, 50 - 55
• Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA / F. Huemer, T. Polzer, A. Steininger / in: "2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)", issued by: IEEE CS Press; IEEE Xplore Digital Library, 2018, ISBN: 978-1-5386-5754-6, 141 - 146
• Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication / F. Huemer, A. Steininger / in: "2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)", issued by: IEEE CS Press; IEEE Xplore Digital Library, 2018, ISBN: 978-1-5386-5883-3, 17 - 25
• State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration / M. Schütz, A. Steininger, F. Huemer, J. Lechner / in: "2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)", issued by: IEEE CS Press; IEEE Xplore Digital Library, 2018, ISBN: 978-1-5386-8398-9, 6 pages

2017

• A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study / M. Andjelkovic, M. Krstic, R. Kraemer, V. S. Veeravalli, A. Steininger / Talk: The 26th IEEE Asian Test Symposium (ATS´17), Taipei, Taiwan; 2017-11-27 - 2017-11-30; in: "Proceedings of the 26th IEEE Asian Test Symposium (ATS´17)", (2017), 1 - 6
• Setup for an Experimental Study of Radiation Effects in 65nm CMOS / B. Fritz, V. S. Veeravalli, A. Steininger, V. Simek / Talk: 20th Euromicro Conference on Digital System Design, Wien; 2017-08-30 - 2017-09-01; in: "Proceedings of the 20th Euromicro Conference on Digital System Design", (2017), 329 - 336
• Measuring Metastability with Free-Running Clocks / R. Najvirt, T. Polzer, A. Steininger / Talk: 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California; 2017-05-21 - 2017-05-24; in: "Proceedings 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017)", IEEE Computer Society, 10662 Los Vaqueros Circle (2017), ISBN: 978-1-5386-2749-5; Paper ID 37, 7 pages
• Measuring Metastability Using a Time-to-Digital Converter / T. Polzer, F. Huemer, A. Steininger / Talk: 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Dresden; 2017-04-19 - 2017-04-21; in: "Proceedings 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", IEEE Service Center, (2017), ISBN: 978-1-5386-0471-7; Paper ID 55, 6 pages
• A Model for the Metastability Delay of Sequential Elements / T. Polzer, A. Steininger / Journal of Circuits, Systems, and Computers, 26 (2017), 8; 174001001 - 174001022
• A versatile architecture for long-term monitoring of single-event transient durations / V. S. Veeravalli, A. Steininger, U. Schmid / Microprocessors and Microsystems, 53 (2017), C; 130 - 144
• Novel Trends in Design & Test / A. Steininger, A. Pawlak, V. Stopjakova / Journal of Circuits, Systems, and Computers, 26 (2017), 80 pages

2016

• A Programmable Delay Line for Metastability Characterization in FPGAs / T. Polzer, F. Huemer, A. Steininger / Talk: 24th Austrian Workshop on Microelectronics (Austrochip), Villach; 2016-10-19; in: "Proceedings 24th Austrian Workshop on Microelectronics", (2016), 6 pages
• A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes / F. Huemer, J. Lechner, A. Steininger / Poster: 2016 IEEE International Conference on Computer Design, Phoenix, Arizona, USA; 2016-10-03 - 2016-10-05; in: "Proceedings 2016 IEEE International Conference on Computer Design", (2016), ISBN: 978-1-5090-5142-7; 392 - 395
• Design and Physical Implementation of a Target ASIC for SET Experiments / V. S. Veeravalli, A. Steininger / Poster: 2016 Euromicro Conference on Digital System Design (DSD), Limassol, Portugal; 2016-08-31 - 2016-09-02; in: "Proc. 2016 Euromicro Conference on Digital System Design (DSD)", IEEE, (2016), ISBN: 978-1-5090-2817-7; 694 - 697
• Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? / A. Steininger, R. Najvirt, J. Maier / Talk: 2016 Euromicro Conference on Digital System Design (DSD), Limassol, Portugal; 2016-08-31 - 2016-09-02; in: "2016 Euromicro Conference on Digital System Design (DSD)", IEEE, (2016), ISBN: 978-1-5090-2817-7; 372 - 379
• Study of a Delayed Single-Event Effect in the Muller C-element / V. S. Veeravalli, A. Steininger / Poster: 21st IEEE European Test Symposium, Amsterdam; 2016-05-24 - 2016-05-27; in: "Proc 21st IEEE European Test Symposium", (2016), ISBN: 978-1-4673-9659-2
• The Metastable Behavior of a Schmitt-Trigger / A. Steininger, J. Maier, R. Najvirt / Talk: 22nd IEEE International Symposium on Asynchronous Circuits and Systems, Porto Alegre -- Brazil; 2016-05-08 - 2016-05-11; in: "2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)", IEEE Computer Society Conference Publishing Services (CPS), (2016), ISBN: 978-1-4673-9007-1; 57 - 64
• A General Approach for Comparing Metastable Behavior of Digital CMOS Gates / T. Polzer, A. Steininger / Talk: 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Kosice, Slovakia; 2016-04-20 - 2016-04-22; in: "Proc 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2016), ISBN: 978-1-5090-2467-4; 6 pages
• Fifty Shades of Synchrony / A. Steininger / in: "This Asynchronous Woirld", A. Mokhov (ed.); Newcastle University, Newcastle upon Tyne, 2016, (invited), ISBN: 978-0-7017-0257-1, 294 - 300

2015

• Can we trust SET Injection Models? / V. S. Veeravalli, A. Steininger / Talk: MEDIAN Finale Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, Tallinn, Estonia; 2015-11-10 - 2015-11-11; in: "MEDIAN Finale Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale", (2015), 6 pages
• Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes / J. Lechner, A. Steininger, F. Huemer / Talk: 33rd IEEE International Conference on Computer Design, New York City, USA; 2015-10-19 - 2015-10-21; in: "33rd IEEE International Conference on Computer Design", (2015), 8 pages
• Revisiting Sorting Network based Completion Detection for 4 Phase Delay Insensitive Codes / F. Huemer, M. Schütz, A. Steininger / Talk: Austrochip Workshop on Microelectronics, Wien; 2015-09-28; in: "Austrochip Workshop on Microelectronics", (2015), 6 pages
• A Practical Comparison of 2-Phase Delay Insensitve Communication Protocols / M. Schütz, F. Huemer, A. Steininger / Talk: Austrochip Workshop on Microelectronics, Wien; 2015-09-28; in: "Austrochip Workshop on Microelectronics", (2015), 6 pages
• A Versatile and Reliable Glitch Filter for Clocks / R. Najvirt, A. Steininger / Talk: 25th International Workshop on Power and Timing Modeling, Optimization and Simulation, Salvador, Brasilien; 2015-09-01 - 2015-09-04; in: "25th International Workshop on Power and Timing Modeling, Optimization and Simulation", (2015), 8 pages
• Reliable and Continuous Measurement of SET Pulse Widths / V. S. Veeravalli, A. Steininger / Talk: 18th Euromicro Conference on Digital System Design, Funchal, Portugal; 2015-08-26 - 2015-08-28; in: "18th Euromicro Conference on Digital System Design", (2015), 8 pages
• Enhanced Metastability Characterization based on AC Analysis / T. Polzer, A. Steininger / Talk: 18th Euromicro Conference on Digital System Design, Funchal, Portugal; 2015-08-26 - 2015-08-28; in: "18th Euromicro Conference on Digital System Design", (2015), 9 pages
• Measuring the Distribution of Metastable Upsets over Time / T. Polzer, A. Steininger / Talk: 18th Euromicro Conference on Digital System Design, Funchal, Portugal; 2015-08-26 - 2015-08-28; in: "Measuring the Distribution of Metastable Upsets over Time", (2015), 8 pages
• A Pausible Clock with Crystal Oscillator Accuracy / R. Najvirt, A. Steininger / Talk: 22nd European Conference on Circuit Theory and Design, Trondheium, Norwegen; 2015-08-24 - 2015-08-26; in: "22nd European Conference on Circuit Theory and Design", (2015), Paper ID 67, 4 pages
• How to Synchronize a Pausible Clock to a Reference / R. Najvirt, A. Steininger / Talk: 21st IEEE International Symposium on Asynchronous Circuits and Systems, Mountain View, CA; 2015-05-04 - 2015-05-06; in: "21st IEEE International Symposium on Asynchronous Circuits and Systems", (2015), 8 pages
• Containment of Metastable Voltages in FPGAs / R. Najvirt, T. Polzer, F. Beck, A. Steininger / Talk: 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Belgrad; 2015-04-22 - 2015-04-24; in: "18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2015), 6 pages
• A Composable Real-Time Architecture for Replicated Railway Applications / S. Resch, A. Steininger, C. Scherrer / Journal of Systems Architecture, 61 (2015), 9; 472 - 485
• On the Appropriate Handling of Metastable Voltages in FPGAs / T. Polzer, R. Najvirt, F. Beck, A. Steininger / Journal of Circuits, Systems, and Computers, 25 (2015), 3; 1640020-1 - 1640020-25
• Building reliable systems-on-chip in nanoscale technologies / A. Steininger, H. Zimmermann, A. Jantsch, M. Hofbauer, U. Schmid, K. Schweiger, V. S. Veeravalli / E&I Elektrotechnik und Informationstechnik, 132 (2015), 6; 301 - 306
• Fault-tolerant Distributed Systems in Hardware / D. Dolev, M Függer, C. Lenzen, U. Schmid, A. Steininger / Bulletin of the EATCS, 2 (2015), 116; 43 pages

2014

• Exploring the State Dependent SET Sensitivity of Asynchronous Logic - The Muller-Pipeline Example / A. Steininger, V. S. Veeravalli, D. Alexandrescu, E. Costenaro, L. Anghel / Talk: 2014 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea; 2014-10-19 - 2014-10-22; in: "Proceedings of the 2014 32nd IEEE International Conference on Computer Design (ICCD)", IEEE, (2014), ISBN: 978-1-4799-6492-5; Paper ID 69, 7 pages
• Long Term On-Chip Monitoring of SET Pulsewidths in a Fully Digital ASIC / V. S. Veeravalli, A. Steininger / Talk: 22nd Austrian Workshop on Microelectronics, Graz; 2014-10-09; in: "Proceedings of the 22nd Austrian Workshop on Micorelectronics", IEEE, (2014), ISBN: 978-1-4799-7243-2; Paper ID 24, 6 pages
• Equivalence of Clock Gating and Synchronization with Applicability to GALS Communication / R. Najvirt, A. Steininger / Talk: 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, Isles Balears, Spain; 2014-09-29 - 2014-10-01; in: "Proceedings of the 24th International Workshop on Power and Timing Modeling, Optimization and Simulation", IEEE, (2014), ISBN: 978-1-4799-5412-4; Paper ID 29, 8 pages
• Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic / J. Maier, A. Steininger / Talk: 17th Symposium on Design and Diagnosis of Electronic Circuits and Systems (DDECS 2014), Warschau, Polen; 2014-04-23 - 2014-04-25; in: "Design and Diagnostics of Electronic Circuits Systems (DDECS), 2014 IEEE 17th International Symposium on", (2014), 6 pages
• Diagnosis of SET Propagation in Combinational Logic under Dynamic Operation / V. S. Veeravalli, A. Steininger / Poster: 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10), Stanford University, USA; 2014-04-01 - 2014-04-02; in: "Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10)", (2014), 6 pages
• Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum / L. Anghel, V. S. Veeravalli, D. Alexandrescu, A. Steininger, K. Schneider, E. Costenaro / Talk: 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10), Stanford University, USA; 2014-04-01 - 2014-04-02; in: "Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10)", (2014), 6 pages
• A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments / S. Naqvi, A. Steininger / Talk: Design Automation &Test in Europe Conference and Exhibition 2014 (DATE 14), Dresden, Deutschland; 2014-03-24 - 2014-03-28; in: "Proceedings Design Automation &Test in Europe", (2014), ISBN: 978-3-9815370-2-4; 6 pages
• Architecture for Monitoring SET Propagation in 16-bit Sklansky Adder / V. S. Veeravalli, A. Steininger / Poster: 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA; 2014-03-10 - 2014-03-12; in: "Proceedings 15th International Symposium & Exhibit on Quality Electronic Design", (2014), ISBN: 978-1-4799-3946-6; 8 pages
• Measuring SET Pulsewidths in Logic Gates using Digital Infrastructure / V. S. Veeravalli, A. Steininger, U. Schmid / Talk: 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA; 2014-03-10 - 2014-03-12; in: "Proceedings 15th International Symposium & Exhibit on Quality Electronic Design", (2014), ISBN: 978-1-4799-3946-6; 7 pages
• Protection of Muller-Pipelines from Transient Faults / S. Naqvi, J. Lechner, A. Steininger / Talk: 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA; 2014-03-10 - 2014-03-12; in: "Proceedings 15th International Symposium & Exhibit on Quality Electronic Design", (2014), ISBN: 978-1-4799-3946-6; 9 pages
• Runtime verification of microcontroller binary code / T. Reinbacher, J. Brauer, M. Horauer, A. Steininger, S. Kowalewski / Science of Computer Programming, 80 (2014), 109 - 129
• Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip / D. Dolev, M Függer, M. Posch, U. Schmid, A. Steininger, C. Lenzen / Journal of Computer and System Sciences, 80 (2014), 4; 860 - 900

2013

• Software Composability and Mixed Criticality for Triple Modular Redundant Architectures / S. Resch, A. Steininger, C. Scherrer / Talk: SASSUR Workshop 2013, Toulouse; 2013-09-24; in: "Proceedings of the 2013 SASSUR Workshop", (2013), 4 pages
• SET Propagation in Micropipelines / T. Polzer, A. Steininger / Talk: 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013), Karlsruhe; 2013-09-09 - 2013-09-11; in: "23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013)", (2013), 8 pages
• Metastability Characterization for Muller C-Elements / T. Polzer, A. Steininger / Talk: 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013), Karlsruhe; 2013-09-09 - 2013-09-11; in: "23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS2013)", (2013), 8 pages
• Digital Late-Transition Metastability Simulation Model / T. Polzer, A. Steininger / Talk: 16th Euromicro Conference on Digital System Design (DSD 2013), Santander; 2013-09-04 - 2013-09-06; in: "Proceedings of the 16th Euromicro Conference on Digital System Design", (2013), 8 pages
• Single Event Transient Pulse Shape Measurements by On-chip Sense Amplifiers in a Single Inverter for Intermediate Input States under Alpha Particle Irradiation / M. Hofbauer, K. Schweiger, W. Gaberl, H. Zimmermann, U. Giesen, F. Langner, U. Schmid, A. Steininger / Poster: IEEE Nuclear and Space Radiation Effects Conference (NSREC), San Francisco, California (USA); 2013-07-08 - 2013-07-12
• Particle Strikes in C-Gates: Relevance of SET Shapes / R. Najvirt, V. S. Veeravalli, A. Steininger / Talk: 2nd Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, Avignon; 2013-05-30 - 2013-05-31; in: "Proceedings of the MEDIAN Workshop 2013", (2013), 4 pages
• FATAL+HEX: Fault-Tolerant Self-Stabilizing Clock Generation+Distribution / D. Dolev, M Függer, M. Hofstätter, C. Lenzen, M. Perner, M. Posch, U. Schmid, M. Sigl, A. Steininger / Poster: Poster Session at the CSAIL Industry Affiliates Program (CSAIL-IAP) Annual Meeting, Cambridge, MA, USA; 2013-05-29 - 2013-05-30
• Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs / R. Najvirt, S. Naqvi, A. Steininger / Talk: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, CA; 2013-05-19 - 2013-05-22; in: "Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on", (2013), ISSN: 1522-8681; 9 pages
• An Approach for Efficient Metastability Characterization of FPGAs through the Designer / T. Polzer, A. Steininger / Talk: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, CA; 2013-05-19 - 2013-05-22; in: "19th IEEE International Symposium on Asynchronous Circuits and Systems", (2013), ISSN: 1522-8681; 9 pages
• An SET Tolerant Tree Arbiter Cell / S. Naqvi, A. Steininger, J. Lechner / Talk: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, CA; 2013-05-19 - 2013-05-22; in: "Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on", (2013), ISSN: 1522-8681; 9 pages
• A Multi-Credit Flow Control Scheme for Asynchronous NoCs / S. Naqvi, R. Najvirt, A. Steininger / Talk: 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Karoly Vary, Czech Republic; 2013-04-08 - 2013-04-10; in: "Proc. 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2013), 6 pages
• Performance of Radiation Hardening Techniques under Voltage and Temperature Variations / V. S. Veeravalli, A. Steininger / Talk: 2013 IEEE Aerospace Conference, Big Sky, Montana, USA; 2013-03-02 - 2013-03-09; in: "Proc. 2013 IEEE Aerospace Conference", (2013), 6 pages
• Supply Voltage Dependent On-Chip Single-Event Transient Pulse Shape Measurements in 90-nm Bulk CMOS Under Alpha Irradiation / M. Hofbauer, K. Schweiger, H. Zimmermann, U. Giesen, F. Langner, U. Schmid, A. Steininger / IEEE Transactions on Nuclear Science, 60 (2013), 4; 2640 - 2646
• An infrastructure for accurate characterization of single-event transients in digital circuits / V. S. Veeravalli, T. Polzer, U. Schmid, A. Steininger, M. Hofbauer, K. Schweiger, H. Dietrich, K. Schneider-Hornstein, H. Zimmermann, K. Voss, B. Merk, M. Hajek / Microprocessors and Microsystems, 37 (2013), 772 - 791

2012

• LFSR Implementation Using C-Elements / V. S. Veeravalli, A. Steininger / Talk: MEMICS 2012, Znjomo, Czechia; 2012-10-25 - 2012-10-28; in: "MEMICS 2012", (2012), 73 - 83
• Reliable Gateway for Radiation Experiments on a VLSI Chip / B. Fritz, V. S. Veeravalli, A. Steininger / Poster: Austrochip 2012, Graz, Austria; 2012-10-10; in: "Austrochip 2012", (2012), 65 - 70
• Supply Voltage Dependent On-chip Single Event Transient Pulse Shape Measurements in 90 nm Bulk CMOS under Alpha Irradiation / M. Hofbauer, K. Schweiger, H. Zimmermann, U. Giesen, F. Langner, U. Schmid, A. Steininger / Poster: 21st European Conference on Radiation and its Effects on Components and Systems (RADECS'12), Biarritz, FRANCE; 2012-09-24 - 2012-09-28; in: "Proceedings 21st European Conference on Radiation and its Effects on Components and Systems (RADECS'12)", (2012)
• A Runtime Verification Unit for Microcontrollers / T. Reinbacher, M. Horauer, A. Steininger / Talk: System, Software, SoC and Silicon Debug Conference (S4D), 2012, Vienna, Austria; 2012-09-19 - 2012-09-20; in: "System, Software, SoC and Silicon Debug Conference (S4D), 2012", (2012), ISSN: 2114-3684; 1 - 6
• Protecting an Asynchronous NoC against Transient Channel Faults / S. Naqvi, V. S. Veeravalli, A. Steininger / Talk: DSD 2012 (Euromicro Conference on Digital System Design), Cesme, Izmir, Turkey; 2012-09-05 - 2012-09-08; in: "Proc. of 15th Euromicro Conference on Digital System Design", (2012), 8 pages
• Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip / V. S. Veeravalli, A. Steininger, U. Schmid, T. Polzer / Talk: 15th Euromicro Symposium on Digital System Design: Architectures, Methods and Tools (DSD 2012), Izmir, Turkey; 2012-09-05 - 2012-09-08; in: "Proceedings 15th Euromicro Symposium on Digital System Design: Architectures, Methods and Tools (DSD'12)", (2012), 8 - 17
• Muller C-Element Metastability Containment / T. Polzer, A. Steininger, J. Lechner / Talk: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2012, Newcastle upon Tyne; 2012-09-04 - 2012-09-06; in: "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation", Lecture Notes in Computer Science, 7606 (2013), ISBN: 978-3-642-36156-2; 103 - 112
• Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating through a 90 nm Bulk CMOS Inverter Chain / M. Hofbauer, K. Schweiger, H. Dietrich, H. Zimmermann, K.O. Voss, B Merk, U. Schmid, A. Steininger / Poster: Nuclear and Space Radiation Effects Conference (NSREC), Miami, FL, USA; 2012-07-16 - 2012-07-20
• Parallel Runtime Verification of Temporal Properties for Embedded Software / T. Reinbacher, J. Geist, P. Moosbrugger, M. Horauer, A. Steininger / Talk: Mechatronics and Embedded Systems and Applications (MESA), 2012 IEEE/ASME International Conference on, Suzhou, China; 2012-07-08 - 2012-07-10; in: "Mechatronics and Embedded Systems and Applications (MESA), 2012 IEEE/ASME International Conference on", (2012), ISBN: 978-1-4673-2347-5; 224 - 231
• Monitoring Single Event Transient Effects in Dynamic Mode / V. S. Veeravalli, A. Steininger / Talk: 1st Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2012), Annecy, France; 2012-05-28 - 2012-06-01; in: "1st Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2012)", (2012), 51 - 54
• Radiation-Tolerant Combinational Gates - An Implementation Based Comparison / V. S. Veeravalli, A. Steininger / Talk: 15th IEEE International Conference on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2012), Tallinn, Estonia; 2012-04-18 - 2012-04-20; in: "Design and Diagnostics of Electronic Circuits Systems (DDECS), 2012 IEEE 15th International Symposium on", (2012), 115 - 120
• Efficient Radiation-Hardening of a Muller C-Element / V. S. Veeravalli, A. Steininger / Talk: 2012 Single Event Effects Symposium (SEE 2012), San Diego, USA; 2012-04-03 - 2012-04-05; in: "2012 Single Event Effects Symposium", (2012)
• Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach / P. Milbredt, M. Glass, M. Lukasiewycz, A. Steininger, J. Teich / Talk: Design, Automation & Test in Europe Conference & Exhibition (DATE 2012), Dresden, Germany; 2012-03-12 - 2012-03-16; in: "Design, Automation & Test in Europe Conference & Exhibition (DATE 2012) Proceedings", EDAA, (2012), ISBN: 978-3-9810801-8-6; 276 - 279
• Pulse Shape Measurements by On-chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain / M. Hofbauer, K. Schweiger, H. Dietrich, H. Zimmermann, K.O. Voss, B Merk, U. Schmid, A. Steininger / IEEE Transactions on Nuclear Science, vol 59 (2012), 2778 - 2784

2011

• Automated test-trace inspection for microcontroller binary code / T. Reinbacher, J. Brauer, D. Schachinger, A. Steininger, S. Kowalewski / Talk: 2nd International Conference on Runtime Verification (RV 2011), San Francisco; 2011-09-27 - 2011-09-30; in: "Runtime Verification", (2011), 239 - 244
• Past time LTL runtime verification for microcontroller binary code / T. Reinbacher, J. Brauer, M. Horauer, A. Steininger, S. Kowalewski / Talk: FMICS 2011, Trento; 2011-08-29 - 2011-08-30; in: "Formal Methods for Industrial Critical Systems", Springer Berlin / Heidelberg, (2011), ISBN: 978-3-642-24430-8; 37 - 51
• Hardware support for efficient testing of embedded software / T. Reinbacher, A. Steininger, T. Müller, M. Horauer, J. Brauer, S. Kowalewski / Talk: The 7th ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications, Washington; 2011-08-29 - 2011-08-31; in: "International Conference on Mechatronic and Embedded Systems and Applications", ASME, (2011)
• VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation / A. Steininger, G. Fuchs / Journal of Electrical and Computer Engineering, Clock/Frequency Generation Circuits and Systems (2011), 936712; 23
• Replicated processors on a single die - How independently do they fail? / A. Steininger, P Tummeltshammer / Journal e&i: Elektrotechnik und Informationstechnik, 128 (2011), 245 - 250

2010

• Test-Case Generation for Embedded Binary Code Using Abstract Interpretation / T. Reinbacher, J. Brauer, M. Horauer, A. Steininger, S. Kowalewski / Talk: MEMICS 2010 (Mathematical and Engineering Methods in Computer Science), Mikulov, Czech Republic; 2010-10-22 - 2010-10-24; in: "MEMICS proceedings", (2010), 151 - 158
• Implementation of Self-Healing Asynchronous Circuits at the Example of a Video-Processing Algorithm / W. Friesenbichler, T. Panhofer, A. Steininger / Talk: WSDN 2010 (4th Workshop on Dependable and Secure Nanocomputing, Chicago, IL, USA; 2010-06-28 - 2010-07-01; in: "WSDN - Full Program", IEEE Computer Socitey, (2010), ISBN: 9781424477289; 129 - 134
• Reliability Estimation and Experimental Results of a Self-Healing Asynchronous Circuit: A Case Study / W. Friesenbichler, T. Panhofer, A. Steininger / Talk: NASA/ESA 2010 (Conference on Adaptive Hardware and Systems), Anaheim, CA, USA; 2010-06-15 - 2010-06-18; in: "NASA/ESA 2010 Proceedings", IEEE Computer Society, (2010), ISBN: 9781424458882; 97 - 104
• Enhancing Pipelined Processor Architectures with Fast Autonomous Recovery of Transient Faults / M. Jeitler, J. Lechner, A. Steininger / Poster: DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria; 2010-04-14 - 2010-04-16; in: "13th IEEE International Symposium On Design And Diagnostics Of Electronic Cicruits And Systems", IEEE Computer Society, (2010), ISBN: 9781424466108; 233 - 236
• A Deterministic Approach for Hardware Fault Injection in Asynchronous QDI Logic / W. Friesenbichler, T. Panhofer, A. Steininger / Talk: DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria; 2010-04-14 - 2010-04-16; in: "13th IEEE International Symposium On Design And Diagnostics Of Electronic Cicruits And Systems", IEEE, (2010), ISBN: 9781424466108; 317 - 322

2009

• A Metastability-Free Multi-synchronous Communication Scheme for SoCs / T. Polzer, T. Handl, A. Steininger / Talk: SSS 2009 (Symposium on Stabilization, Safety, and Security of Distributed Systems), Lyon, France; 2009-11-03 - 2009-11-06; in: "Stabilization, Safety, and Security of Distribiuted Systems", Springer, 5873/2009 (2009), ISBN: 978-3642051173; 578 - 592
• Error Containment in the Presence of Metastability / A. Steininger / Talk: Dagstuhl Seminar 08371 : Fault-Tolerant Distributed Algorithms on VLSI Chips, Dagstuhl, Germany (invited); 2009-09-07 - 2009-09-10; in: "Fault-Tolerant Distributed Algorithms on VLSI Chips", Leibniz Zentrum Informatik, 08371 (2009), ISSN: 1862-4405; ?
• On the Risk of Fault Coupling over the Chip Substrate / P Tummeltshammer, A. Steininger / Talk: DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece; 2009-08-27 - 2009-08-29; in: "12th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - Architectures, Methods and Tools - DSD2009", IEEE Computer Society, (2009), ISBN: 9780769537825; 325 - 332
• Soft Error Tolerant Asynchronous Circuits based on Dual Redundant Four State Logic / W. Friesenbichler, A. Steininger / Talk: DSD 2009 (Euromicro Conference on Digital System Design), Patras, Greece; 2009-08-27 - 2009-08-29; in: "12th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - Architectures, Methods and Tools - DSD 2009", IEEE Computer Society, (2009), ISBN: 9780769537825; 100 - 107
• On the Stability and Robustness of Non-Synchronous Circuits with Timing Loops / M Függer, G. Fuchs, A. Steininger / Talk: WSDN 2009 (Workshop on Dependable and Secure Nanocomputing, Estoril, Lisbon, Portugal; 2009-06-29 - 2009-06-30; in: "WSDN 2009", Springer, (2009), ISBN: 9781424444212; 45 - 50
• Power Supply Induced Common Cause Faults - Experimental Assessment of Potential Countermeasures / P Tummeltshammer, A. Steininger / Talk: DSN 2009 (International Conference on Dependable Systems and Networks), Estoril, Portugal; 2009-06-29 - 2009-07-02; in: "DSN 2009 - Full Program", Springer, (2009), ISBN: 9781424444212; 449 - 457
• On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme / G. Fuchs, M Függer, A. Steininger / Talk: ASYNC 2009 (International Symposium on Asynchronous Circuits and Systems), Chapel Hill, North Carolina; 2009-05-17 - 2009-05-20; in: "ASYNC 2009", IEEE Computer Society, (2009), ISSN: 1522-8681; 127 - 136
• Remote Measurement of Local Oscillator Drifts in FlexRay Networks / E. Armengaud, A. Steininger / Talk: DATE 2009 (Design, Automation and Test in Europe), Nice, France; 2009-04-20 - 2009-04-24; in: "DATE09", Springer, (2009), ISBN: 9783981080155; 1082 - 1087
• On the Role of the Power Supply as an Entry for Common Cause Faults - An Experimental Analysis / P Tummeltshammer, A. Steininger / Talk: DDECS 2009 (Design and Diagnostics of Electronic Circuits and Systems), Liberec, Czech Republic; 2009-04-15 - 2009-04-17; in: "2009 IEEE Design and Diagnostics of Electronic Circuits and Systems", IEEE, 00 (2009), ISBN: 9781424433414; 152 - 157
• Is Asynchronous Logic More Robust Than Synchronous Logic? / B. Rahbaran, A. Steininger / IEEE Transactions on Dependable and Secure Computing, 6 (2009), 4; 282 - 294
• Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - A Combined Formal and Experimental Approach / M Függer, A. Steininger, E. Armengaud / IEEE Transactions on Industrial Informatics, 5 (2009), 2; 132 - 145

2008

• Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip / G. Fuchs, M Függer, U. Schmid, A. Steininger / Talk: 11th EUROMICRO Conference on Digital System Design (DSD 2008), Parma, Italien; 2008-09-03 - 2008-09-05; in: "11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008.", IEEE, (2008), ISBN: 978-0-7695-3277-6; 242 - 249
• An Investigation of the Clique Problem in Flex Ray / P. Milbredt, M. Horauer, A. Steininger / Talk: SIES´2008 Third international symposium on industrial embedded systems, Montpellier - La Grande Motte, France; 2008-08-11 - 2008-08-13; in: "International Symposium on Industrial Embedded Systems, 2008.", (2008), ISBN: 978-1-4244-1995-1; 200 - 207
• Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras / K. Ambrosch, M. Humenberger, W. Kubinger, A. Steininger / Talk: IEEE Conference on Computer Vision and Pattern Recognition, 2008. CVPR '08, Anchorage, Alaska, USA; 2008-06-23 - 2008-06-28; in: "CVPR Workshops 2008. IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, 2008.", (2008), ISBN: 978-1-4244-2339-2; 1 - 8
• Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks / P. Milbredt, A. Steininger, M. Horauer / Talk: IEEE International Workshop on Electronic Design, Test and Applications, Hong-Kong; 2008-05-23 - 2008-05-25; in: "4th IEEE International Symposium on Electronic Design, Test and Applications, 2008. DELTA 2008.", (2008), ISBN: 978-0-7695-3110-6; 533 - 538
• Safe deterministic replay for stimulating the clock synchronization algorithm in time-triggered systems / E. Armengaud, M Függer, A. Steininger / Talk: WFCS, Dresden, Germany; 2008-05-20 - 2008-05-23; in: "IEEE International Workshop on Factory Communication Systems, 2008. WFCS 2008.", (2008), ISBN: 978-1-4244-2349-1; 277 - 286
• Automated Generation of Explicit Connectors for Component Based Hardware/Software Interaction in Embedded Real-Time Systems / W. Forster, C. Kutschera, A. Steininger, K. Göschka / Talk: 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS 2008), (IPDPS 2008), Miami, Florida, USA; 2008-04-14; in: "Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS 2008), (IPDPS 2008)", IEEE Computer Society, (2008), ISBN: 978-1-4244-1694-3; 1 - 8
• Exploring the Usefulness of the Gate-level Stuck-at Fault Model for Muller C-Elements / J. Grahsl, T. Handl, A. Steininger / Poster: 20. GI/ITG/GMM Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen, Wien; 2008-02-24 - 2008-02-26; in: "20. Workshop Testmethoden und Vuverlässigkeit von Schaltungen und Systemen", (2008), 165 - 169
• Towards a Systematic Test for Embedded Automotive Communication Systems / E. Armengaud, A. Steininger, M. Horauer / IEEE Transactions on Industrial Informatics, 4 (2008), 3; 145 - 208

2007

• A Fail-Silent Reconfigurable Superscalar Processor / T. Kottke, A. Steininger / Talk: 13th Pacific Rim International Symposium on Dependable Computing (PRDC 07), Melbourne; 2007-12-17 - 2007-12-19; in: "13th Pacific Rim International Symposium on Dependable Computing (PRDC'07), Melbourne", (2007), 232 - 239
• Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit / T. Handl, A. Steininger, G. Kempf / Talk: International Design and Test Workshop (IDT), Kairo; 2007-12-16 - 2007-12-18; in: "Proceedings IDT'07 - The Second International Design and Test Workshop", (2007), 115 - 119
• SAFE - A Scalable Environment for Automated Transistor Level Fault Effect Analysis / J. Grahsl, T. Handl, A. Steininger, G. Kempf / Talk: Austrochip, Graz; 2007-10-11; in: "Austrochip - Workshop on Microelectronics", (2007), 91 - 98
• The Effect of Quartz Drift on Convergence-Average based Clock Synchronization / E. Armengaud, A. Steininger, A. Hanzlik / Talk: IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), Patras; 2007-09-25 - 2007-09-28; in: "Proceedings of the 12th IEEE Conference on Emerging Technologies and Factory Automation", (2007), 1123 - 1130
• Concepts and Tools for the Test of the Communication Sub-System of Time-Triggered Distributed Embedded Systems / M. Horauer, E. Armengaud, A. Steininger / Talk: International Conference on Design Engineering Technical Conferences & Computers and Information in Engineering (ASME), Las Vegas; 2007-09-04 - 2007-09-07; in: "ASME 2007 International Conference on Design Engineering Technical Conferences & Computers and Information in Engineering", (2007)
• Hardware Implementation of an SAD based stereo vision algorithm / K. Ambrosch, M. Humenberger, W. Kubinger, A. Steininger / Talk: Third IEEE Workshop on Embedded Computer Vision, Minneapolis; 2007-06-23; in: "Proceedings of Third IEEE Workshop on Embedded Computer Vision", (2007)
• Towards a Systematic Design of Fault-Tolerant Asynchronous Circuits / U. Schmid, A. Steininger, H. Veith / Poster: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf, München; 2007-03-26 - 2007-03-28; in: "Fachtagung Zuverlässigkeit und Entwurf", VDE Verlag, (2007), ISBN: 978-3-8007-3023-0; 173 - 174
• Vergleich zweier zwischen Sicherheit und Performanz rekonfigurierbarer Prozessorsysteme / T. Kottke, A. Steininger / Poster: 19. ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Errlangen; 2007-03-11 - 2007-03-13; in: "19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2007)
• An Efficient Test Strategy for a Fault-Tolerant Clock Generator for Systems-on-Chip / T. Handl, A. Steininger, G. Kempf / Talk: 19. ITG/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Errlangen; 2007-03-11 - 2007-03-13; in: "19. Workshop - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2007), 66 - 70
• FIT-IT Projekt DARTS: Dezentrale fehlertolerante Taktgenerierung / U. Schmid, A. Steininger, M. Sust / Elektrotechnik und Informationstechnik (e&i), Heft 1-2 (2007), 3 - 8

2006

• An Efficient Test for a Transition Signalling based Up-/Down-Counter / M Függer, T. Handl, A. Steininger, J. Widder, C. Tögel / Poster: Austrochip, Wien; 2006-10-11; in: "Austrochip Mikroelektroniktagung", (2006), 55 - 62
• Threshold Modules -- Die Schlüsselelemente zur Verteilten Generierung eines Fehlertoleranten Taktes / G. Fuchs, J. Grahsl, U. Schmid, A. Steininger, G. Kempf / Talk: Austrochip, Wien; 2006-10-11; in: "Austrochip Mikroelektroniktagung", (2006), 149 - 156
• Recovery Mechanisms for Dual Core Architectures / C. El Salloum, A. Steininger, P Tummeltshammer / Talk: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT ), Washington DC, USA; 2006-10-04 - 2006-10-06; in: "21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, Proceedings", (2006), ISBN: 0-7695-2706-x; 380 - 388
• VLSI Implementation of a Fault-Tolerant Distributed Clock Generation / M. Ferringer, G. Fuchs, A. Steininger, G. Kempf / Talk: International Symp. on Defect and Fault Tolerance in VLSI-Systems, Arlington; 2006-10-04 - 2006-10-06; in: "The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems", (2006), 563 - 571
• Analysis of Constraints in a Fault-Tolerant Distributed Clock Generation Scheme / G. Fuchs, M Függer, A. Steininger, F. Zangerl / Talk: 3rd International Workshop on Dependable Embedded Systems, Leeds; 2006-10-01; in: "WDES 2006 3rd Workshop on Dependable Embedded Systems", (2006), 22 - 27
• Automatic Parameter Identification in FlexRay Based Automotive Communication Networks / E. Armengaud, A. Steininger / Talk: IEEE International Conference on Emerging Technologies and Factory Automation, Prag; 2006-09-20 - 2006-09-22; in: "11th IEEE International Conference on Emerging Technologies and Factory Automation", (2006), 897 - 904
• Testing the Hardware Implementation of a Distributed Clock Generation Algorithm for SoCs / A. Steininger, T. Handl, G. Fuchs, F. Zangerl / Talk: East-West Design & Test International Workshop (EWDTW'06), Sochi (invited); 2006-09-15 - 2006-09-19; in: "East-West Design & Test International Workshop", (2006), 59 - 64
• Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods / M. Delvai, A. Steininger / Poster: 9th Euromicro Conference on Digital System Design, Dubrovnik; 2006-08-30 - 2006-09-01; in: "9th Euromicro Conference on Digital System Design - Architectures, Methods and Tools", (2006), 131 - 136
• Asynchronous Logic Design - from Concepts to Implementation / M. Delvai, A. Steininger / Talk: The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications, Orlando; 2006-07-20 - 2006-07-23; in: "The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 1", (2006), 81 - 86
• A Practical Comparison of Logic Design Styles / M. Delvai, A. Steininger / Talk: The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications, Orlando; 2006-07-20 - 2006-07-23; in: "The 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications - Volume 3", (2006), 61 - 66
• Pushing the Limits of Remote Online Diagnosis in FlexRay Networks / E. Armengaud, A. Steininger / Talk: IEEE International Workshop on Factory Communication Systems, Torino; 2006-06-27 - 2006-06-30; in: "6th IEEE International Workshop on Factory Communication Systems", (2006)
• Fault-Tolerant Algorithms on SoCs - A case study / A. Steininger, M Függer, U. Schmid, G. Fuchs / Talk: IEEE International Conference on Dependable Systems and Networks, Philadelphia; 2006-06-25 - 2006-06-28; in: "Supplement Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN)", (2006), 190 - 191
• A Reconfigurable Generic Dual-Core Architecture / T. Kottke, A. Steininger / Talk: IEEE International Conference on Dependable Systems and Networks, Philadelphia; 2006-06-25 - 2006-06-28; in: "Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN)", (2006), 45 - 54
• The DARTS project / A. Steininger / Talk: ESA Workshop, Wien; 2006-05
• Implementation of an FPGA-Based Hardware Fault Injector / T. Handl, A. Steininger / Poster: Junior Scientist Conference, Wien; 2006-04-19 - 2006-04-21; in: "Junior Scientist Conference 2006", (2006), 23 - 24
• A Remote and Transparent Approach for the Test and Diagnosis of Automotive Networks / E. Armengaud, A. Steininger / Poster: Junior Scientist Conference, Wien; 2006-04-19 - 2006-04-21; in: "Junior Scientist Conference 2006", (2006)
• Time-Multiplexed Multiple Constant Multiplication / P Tummeltshammer, A. Steininger / Talk: Junior Scientist Conference, Wien; 2006-04-19 - 2006-04-21; in: "Junior Scientist Conference 2006", (2006), 77 - 78
• Ein dynamisch rekonfigurierbarer superskalarer Prozessor mit den Modi Sicherheit und Performanz / A. Steininger, T. Kottke / Talk: 18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Titisee; 2006-03-12 - 2006-03-14; in: "18. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2006), 36 - 40
• Teaching Hardware Software Codesign to Software Engineers / M. Delvai, A. Steininger / Talk: 1st International Workshop on Reconfigurable Computing Education, Karlsruhe; 2006-03-01; in: "International Workshop on Reconfigurable Computing Education", (2006)
• The ECS group's hardware related research activities / A. Steininger / Talk: Firma Freescale, München; 2006-02-17

2005

• ASPEAR - An Asynchronous 16 Bit RISC Processor Core / M. Delvai, A. Steininger / Poster: Siemens PSE Technology Day, Wien; 2005-11-25
• An Efficient Test and Diagnosis Environment for Communication Controllers / E. Armengaud, A. Steininger, M. Horauer / Talk: Austrochip, Wien; 2005-10-06; in: "Austrochip 2005", ???, (2005)
• Design of an Asynchronous Microprocessor with Four-State Logic / M. Delvai, G. Fuchs, T. Handl, W. Huber, A. Steininger / Talk: Austrochip, Wien; 2005-10-06; in: "Austrochip 2005", (2005), 105 - 112
• Efficient Stimulus Genereation for Remote Testing of Distributed Systems - The Flexray Example / E. Armengaud, A. Steininger, M. Horauer / Talk: ETFA, Catania, Italy; 2005-09-19 - 2005-09-22; in: "Proceedings of the 10th IEEE Internationla Conference on Emerging Technologies and Factory Automation", IEEE, I (2005), 763 - 770
• A Flexible Hardware Architecture for Fast Access on Large Non-Volatile Memories / E. Armengaud, F Rothensteiner, A. Steininger, M. Horauer / Talk: IEEE International Workshop on Desgin & Diagnostic of Electronic Circuits and Systems, Sopron; 2005-04-13 - 2005-04-16; in: "Proceedings of IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS) 2005", (2005), 113 - 120
• A Method for Bit Level Test and Diagnosis of Communication Services / E. Armengaud, A. Steininger, M. Horauer / Talk: IEEE International Workshop on Desgin & Diagnostic of Electronic Circuits and Systems, Sopron; 2005-04-13 - 2005-04-16; in: "Proceedings of IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS) 2005", (2005), 69 - 74
• Designoptimierung eines Prozessors mit Eigenfehlererkennung / T. Kottke, A. Steininger / Talk: 17. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen;, Inssbruck; 2005-02-27 - 2005-03-01; in: "16. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen;", (2005), 55 - 59
• A Structured Approach for the Systematic Test of Embedded Automotive Communication Systems / E. Armengaud, F Rothensteiner, A. Steininger, R. Pallierer, M. Horauer, M Zauner / in: "Proceedings International Test Conference 2005", IEEE Computer Society, 2005, ISBN: 0-7803-9039-3, 21 - 28
• A Generic Tool for Systematic Tests in Embedded Automotive Communication Systems / R. Pallierer, M. Horauer, M Zauner, A. Steininger, E. Armengaud, F Rothensteiner / in: "Embedded World 2005", unbekannt, 2005
• Antrag UNI-Infrastruktur III, Embedded Systems Research Cluster / U. Schmid, H. Kopetz, P. Puschner, L. Mayerhofer, A. Steininger, H. Grünbacher, W. Kastner, A. Krall / 2005

2004

• A Dual Core Architecture with Error Containment / T. Kottke, A. Steininger / Talk: East-West Design & Test International Workshop(EWDTW´04), Yalta-Alushta, Crimea, Ukraine; 2004-09-23 - 2004-09-26; in: "East-West Design & Test International Workshop", (2004), ISBN: 966-659-088-3; 102 - 108
• A Layer Model for the Systematic Test of Time-Triggered Automotive Communication Systems / E. Armengaud, A. Steininger, M. Horauer, R. Pallierer / Talk: IEEE International Workshop on Factory Communication Systems, Vienna,Austria; 2004-09-22 - 2004-09-24; in: "IEEE Workshop on Factory Communication Systems (WFCS 04)", IEEE Catalog Number 04TH8777 (2004), ISBN: 0-7803-8734-1; 275 - 283
• Revision and Verification of an Enhanced UART / R. Gallo, M. Delvai, W. Elmenreich, A. Steininger / Talk: IEEE International Workshop on Factory Communication Systems, Vienna, Austria; 2004-09-22 - 2004-09-24; in: "Proceedings of the 2004 IEEE International Workshop on Factory Communication Systems", IEEE, (2004), ISBN: 0-7803-8734-1; 315 - 318
• Design Trade-offs for Systematic Tests of Embedded Communication Systems / E. Armengaud, A. Steininger, M. Horauer, R. Pallierer / Talk: IEEE International Conference on Dependable Systems and Networks, Florence, Italy; 2004-07-28 - 2004-08-01; in: "International Conference on Dependable Systems and Networks (DSN 2004)", (2004), 118 - 119
• Real-time Fault Injection with Signal-Flip model by FIDYCO / B. Rahbaran, A. Steininger / Talk: IEEE International Conference on Dependable Systems and Networks, Florence, Italy; 2004-06-28 - 2004-07-01; in: "DSN 2004 Supplement", IEEE Computer Society, Supplemental (2004), 70 - 71
• Embedded Real-Time-Tracer --An Approach with IDE / B. Rahbaran, M Függer, A. Steininger / Talk: Workshop on Intelligent Solutions in Embedded Systems, Austria, Graz; 2004-06-25; in: "Proceedings of the Second Workshop on Intelligent Solutions in Embedded Systems", (2004), ISBN: 3-902463-00-7; 25 - 35
• A Fail-Silent Memory for Automotive Applications / A. Steininger, T. Kottke / Talk: European Test Symposium, Ajaccio,Corsica,France; 2004-05-23 - 2004-05-26; in: "9th European Test Symposium", (2004), 253 - 258
• A Monitoring Concept for an Automotive Distributed Network - The FlexRay Example / E. Armengaud, A. Steininger, M. Horauer, R. Pallierer, H. Friedl / Talk: 7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2004), Stara Lesna, Slovakia; 2004-04-18 - 2004-04-21; in: "Proceedings of the 7th Workshop on Design and Diognostics of Electronic Circuits and Systems", (2004), ISBN: 80-969117-9-1; 173 - 178
• A Generic Dual-Core Architecture / T. Kottke, A. Steininger / Talk: 7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2004), Stara Lesna, Slovakia; 2004-04-18 - 2004-04-21; in: "7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2004)", (2004), ISBN: 80-969117-9-1; 159 - 166
• Embedded Systems im Auto - Ein Vorbild für die Bahn? / A. Steininger / Talk: Tagung, TU-Wien, Prechtlsaal; 2004-03-11; in: "Intelligenz im Schienenverkehr: Sicherheitsstandarts und effiziente Kapatzitätsnutzung", (2004), #
• Concurrent Checking eines Adressdecoders / A. Steininger, T. Kottke / Talk: 16. ITG/GI/GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Dresden, Germany; 2004-02-29 - 2004-03-02; in: "GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", (2004), 25 - 29
• Monitoring and Fault Injection of X-by-Wire Communication Networks / R. Pallierer, M. Horauer, A. Steininger / Talk: Entwicklerforum Design & Elektronik: Drahtlose und drahtgebundene Netzwerke, Wien; 2004-02-03; in: "Entwicklerforum Design & Elektronik: Drahtlose und drahtgebundene Netzwerke", (2004)
• Built-in Fault Injection in Hardware-- The FIDYCO Example / B. Rahbaran, A. Steininger, T. Handl / Talk: IEEE International Workshop on Electronic Design, Test and Applications, Perth, Australia; 2004-01-28 - 2004-01-30; in: "Second IEEE International Workshop on Electronic Design, Test and Applications", B. Rahbaran, A. Steininger (ed.); IEEE Computer Society Press, Delta 2004, Perth Australia (2004), ISBN: 0-7695-2081-2; 327 - 332
• Embedded Real-Time-Tracer -- An Approach with IDE / B. Rahbaran, M Függer, A. Steininger / Telematik, 3-4 (2004), 16 - 20
• An FPGA based SoC Design for Testing Embedded Automotive Communication Systems employing the FlexRay Protocol / M. Horauer, F Rothensteiner, M Zauner, E. Armengaud, A. Steininger, H. Friedl, R. Pallierer / Poster: Austrochip, Wien; 2004; in: "Austrochip 2004", TU-Wien, (2004), 119 - 123
• Dezentrale Fehlertolerante Taktgenerierung in VLSI Chips / U. Schmid, A. Steininger / Patent: Österreich, submitted: 2004
• Face Recognition on ASICs / P Tummeltshammer, M. Pueschel, A. Steininger, C. Überhuber / Report for Research Report 108/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Constant Multiplication Methods / P Tummeltshammer, M. Pueschel, A. Steininger, C. Überhuber / Report for Research Report 107/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Recovery Mechanisms for Dual Core Architectures / C. El Salloum, A. Steininger / Report for Research Report 100/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• A Reconfigurable Generic Dual Core Architecture / T. Kottke, A. Steininger / Report for Research Report 99/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• A Strategy for Experimental Fault Injection into an Asynchronous Processor / B. Rahbaran, A. Steininger / Report for Research Report 98/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Options for Remote Diagnosis in Automotive Distributed Networks / A. Steininger, M. Horauer, E. Armengaud / Report for Research Report 97/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• A Flexible Hardware Architecture for Fast Access on Large Non-Volatile Memories / E. Armengaud, F Rothensteiner, A. Steininger, M. Horauer / Report for Research Report 96/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Fault Injection -- Requirements and Concepts / E. Armengaud, A. Steininger, M. Horauer / Report for Research Report 95/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Fault Injection Method / E. Armengaud, A. Steininger / Report for Research Report 94/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Automatic Parameter Detection for Communication Protocols / E. Armengaud, A. Steininger / Report for Research Report 91/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Monitoring and Replay hardware -- Requirements and Concepts / E. Armengaud, A. Steininger, M. Horauer / Report for Research Report 89/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Solving the Fundamental Problem of Digital Design -- A Systematic Review of Design Methods / M. Delvai, A. Steininger, W. Huber / Report for Research Report 88/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Code Alternation Logic (CAL): A Novel Efficient Design Approach for Delay-Insensitive Asynchronous Circuits / A. Steininger, M. Delvai, W. Huber / Report for Research Report 87/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Synchronous and Asynchronous Design Methods -- A Hardware Designer's Perspective / A. Steininger, M. Delvai, W. Huber / Report for Research Report 86/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Delay Insensitive Asychronous Pipeline Implementation for Code Alternation Logic / W. Huber, A. Steininger, M. Delvai / Report for Research Report 85/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Code Alternation Logic -- A Novel and Efficient Method for Delay-Insensitive Asynchronous Circuits / A. Steininger, M. Delvai, W. Huber / Report for Research Report 84/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• DARTS - Distributed Algorithms for Robust Tick Synchronization / G. Fuchs, U. Schmid, A. Steininger / Report for Research Report 72/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• EPOCAL - Exploring the Potential of Code Alternation Logic / A. Steininger, T. Handl, G. Fuchs / Report for Research Report 71/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Dezentrale Fehlertolerante Taktgenerierung in VLSI Chips / U. Schmid, A. Steininger / Report for Research Report 69/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004
• Ein Verfahren für das verteilte Generieren eines fehlertoleranten adaptiven Taktes in Hardware / G. Fuchs, U. Schmid, A. Steininger / Report for Research Report 18/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstraße 3, A-1040 Vienna, Austria; 2004

2003

• Towards Virtual Prototyping of Embedded Computer Systems / M. Delvai, M. Jankela, A. Steininger / Poster: The 7th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, Florida; 2003-07-27 - 2003-07-30; in: "Proceedings, Volume I, Information Systems, Technologies and Applications", (2003), 70 - 75
• A Generic Real-time Debugger Architecture / M. Delvai, C. El Salloum, A. Steininger / Talk: World Multiconference on Systemics, cybernetics and Informatics, Orlando, Florida; 2003-07-27 - 2003-07-30; in: "The 7th World Multiconference on Systemics, Cybernetics and Informatics", (2003), 65 - 70
• Processor Support for Temporal Predictability - The SPEAR Design Example / M. Delvai, W. Huber, P. Puschner, A. Steininger / Talk: 15th Euromicro Conference on Real-Time Systems, Porto, Portugal; 2003-07-02 - 2003-07-04; in: "Proceedings of the 15 Euromicro International Conference on Real-Time Systems", (2003), 169 - 176
• Built-in Fault Injectors - The Logical Continuation of BIST? / A. Steininger, B. Rahbaran, T. Handl / Talk: Workshop on Intelligent Solutions in Embedded Systems (WISES'03), Wien; 2003-06-27; in: "Proceeding of the First Workshop on Intelligent Solutions in Embedded Systems", (2003), 187 - 196
• A Transparent Online Memory Test for Simultaneous Detection of Functional Faults and Soft Errors in Memories / K. Thaller, A. Steininger / IEEE Transactions on Reliability, 52 (2003), 4; 413 - 422
• Dealing With Dormant Faults in an Embedded Fault-Tolerant Computer System / C. Scherrer, A. Steininger / IEEE Transactions on Reliability, 52 (2003), 4; 512 - 522

2002

• Using Offline and Online BIST to Improve System Dependability - The TTPC-C Example / A. Steininger, J. Vilanek / Talk: IEEE INTERNATIONAL CONFERENCE ON COMPUTER Design: VLSI in Computers & Processors, Freiburg, Germany; 2002-09-16 - 2002-09-18; in: "Computer Design: VLSI in Computers & Processors", (2002), 277 - 280
• FPGA Implementation of the Time-Triggered Protocol Controller TTPC-C Verification, Design-Experiences and Benefits / J. Vilanek, A. Steininger / Talk: World Multiconference on Systemics, cybernetics and Informatics, Orlando, Florida, USA; 2002-07-14 - 2002-07-18; in: "PROCEEDINGS", (2002), 407 - 412
• An FPGA-Based Development Platform for the virtual Real-Time Processor Component SPEAR / M. Delvai, W. Huber, B. Rahbaran, A. Steininger / Talk: IEEE Design and Diagnostics of Electronic Circuits and Systems (IEEE DDECS 2002), Brno, Czech Republic; 2002-04-17 - 2002-04-19; in: "Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop", (2002), 98 - 105
• Identifying Efficient Combinations of Error Detection Mechanisms Based on Results of Fault-Injection Experiments / A. Steininger, C. Scherrer / IEEE Transactions on Computers, 51 (2002), 2; 235 - 239

2001

• SPEAR-Design-Entscheidungen für den "Scalable Processor for Embeded Application in Real-Time Environment" / M. Delvai, W. Huber, B. Rahbaran, A. Steininger / Talk: Austrochip, wien; 2001-10-12; in: "Die Österreichische Tagnung zum Themenbereich Mikroelektronik", (2001), 25 - 32
• How To Tune the MTTF of a Fault-Tolerant System / A. Steininger, C. Scherrer / Talk: International Symp. on Defect and Fault Tolerance in VLSI-Systems, San Francisco, California, USA; 2001-10-02 - 2001-10-06; in: "PROCEEDINGS", (2001), 251 - 256

2000

• How does Resource Utilization Affect Fault Tolerance? / C. Scherrer, A. Steininger / Talk: International Symp. on Defect and Fault Tolerance in VLSI-Systems, Mt. Fuji, Yamanashi, Japan; 2000-10-02 - 2000-10-06; in: "PROCEEDINGS", (2000), 418 - 425
• Periodic Node Shutdown in a Fail-Silent Architecture - Risk or Rescue? / C. Scherrer, A. Steininger / Poster: World Multiconference on Systemics, cybernetics and Informatics, Orlando, Florida, USA; 2000-07-14 - 2000-07-18; in: "PROCEEDINGS", (2000), 205 - 210
• Vom Lenkrad zum Joystick / A. Steininger, C. Scherrer / Elektrotechnik und Informationstechnik (e&i), 11 (2000), 714 - 720
• Testing and Built-in-Self-Test - A Survey / A. Steininger / Journal of Systems Architecture, 46 (2000), 721 - 747

1998

• Testing of Fault-Tolerant Computers / Habilitation Thesis by A. Steininger / TU Wien, 1998

1995

• The Implementation of the MARS Hardware and Software / J. Reisinger, A. Steininger, G. Leber / in: "Predicatbly Dependable Computing Systems", B. Randell, J. Laprie, H. Kopetz, B. Littlewood (ed.); issued by: ESPRIT Basic Research Series; Springer International Publishing, 1995, ISBN: 3-540-59334-9, 209 - 224

1994

• A Measuring Methodology for Fault-Injection Experiments in Computing Systems / A. Steininger / Österreichischer Kunst- und Kulturverlag, Wien, 1994, ISBN: 3-85437-079-2; 113 pages
• A Measuring Methodology for Fault-Injection Experiments in Computing Systems / Doctoral Thesis by A. Steininger / Supervisor, Reviewer: R. Patzelt, H. Kopetz; 354-02, 1994

 

2021

• Quantitativer Vergleich der Empfindlichkeit von Delay-Insensitiven Design Templates gegenüber transienten Störungen / Master Thesis by P. Behal / Supervisor: A. Steininger; Technische Informatik, 2021; final examination: 2021-06-23
• Implementierung, Erweiterung und Evaluierung von hardwaregestützen CFG-basierenden Programmflußüberwachungen / Master Thesis by M. Telesklav / Supervisor: A. Steininger; Technische Informatik, 2021; final examination: 2021-03-11

2019

• Fault Masking in Synchronous and in Asynchronous Logic - A Comparison / Master Thesis by W. Ramsl / Supervisor: A. Steininger; 191-02, 2019

2018

• SoC FPGA Oszilloskop - Implementierung eines Oszilloskops auf einem FPGA mit eingebettetem Prozessor / Master Thesis by J. Obermüller / Supervisor: A. Steininger; 191-02, 2018
• Operation and Verification Framework for the FRad Experimental ASIC / Master Thesis by B. Fritz / Supervisor: A. Steininger; 191-02, 2018
• COTS FPGAs in Space -- From old Concerns to new Possibilities / Master Thesis by M. Schütz / Supervisor: A. Steininger; 191-02, 2018

2017

• Protecting 4-Phase Delay-Insensitive Communication Against Transient Faults / Master Thesis by F. Huemer / Supervisor: A. Steininger; Technische Informatik, 2017; final examination: 2017-02-20

2016

• ASCARTS Design of an Asynchronous Processor using a High-Level Specification Language / Master Thesis by C. Hermann / Supervisor: A. Steininger, J. Lechner; Institut für Technische Informatik, 2016

2015

• Composability for Fail-Safe Safety-Critical Systems / Doctoral Thesis by S. Resch / Supervisor, Reviewer: A. Steininger, W. Elmenreich; Technische Informatik, 2014; oral examination: 2015-01-26
• Selection and Hardware-Implementation of an Efficient Consensus Algorithm for a Mesochronous System / Master Thesis by A. Heinisch / Supervisor: T. Polzer, A. Steininger; Technische Informatik, 2015; final examination: 2015-01-15

2014

• Building Robust GALS Circuits: Fault-Tolerant and Variation-Aware Design Techniques for Reliable Circuit Operation / Doctoral Thesis by J. Lechner / Supervisor, Reviewer: A. Steininger, J. Sparso; Institut für Technische Informatik, 2014; oral examination: 2014-06-17
• Efficient Interfacing Between Timing Domains / Master Thesis by R. Kutschera / Supervisor: A. Steininger; Technische Informatik, 2014
• Effekte von Stuck-At Faults in Delay-Insensitiver Logik / Master Thesis by C. Trenkwalder / Supervisor: A. Steininger; Technische Informatik, 2014
• Online Test Vector Insertion - A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic / Master Thesis by J. Maier / Supervisor: A. Steininger; Technische Informatik, 2014

2013

• A Non-Blocking Fault-Tolerant Asynchronous Networks-on-Chip Router / Doctoral Thesis by S. Naqvi / Supervisor, Reviewer: A. Steininger, E. Grass, M. Schöberl; Institut für Technische Informatik, 2013
• A Digital Metastability Model for VLSI Circuits / Doctoral Thesis by T. Polzer / Supervisor, Reviewer: A. Steininger, A. Yakovlev; Institut für Technische Informatik, 2013
• Analysis of Embedded Real-Time Systems at Runtime / Doctoral Thesis by T. Reinbacher / Supervisor, Reviewer: A. Steininger, J. Schumann, S. Kowalewski; Institut für Technische Informatik, 2013
• Performance Aware Hardware Runtime Monitors / Master Thesis by A. Hagmann / Supervisor: A. Steininger; Institut für Technische Informatik, 2013
• Design and Evaluation of an AXI4 Bus System / Master Thesis by K. Pados / Supervisor: A. Steininger; Institut für technische Informatik, 2013
• Analysis of the Failure Behavior of Memory Management Units / Master Thesis by O. Hechinger / Supervisor: A. Steininger; Institut für technische Informatik, 2013

2012

• Effects and Mitigation of Transient Faults in Quasi Delay-Insensitive Logic / Doctoral Thesis by W. Friesenbichler / Supervisor, Reviewer: A. Steininger, H. Vierhaus; Institut für Technische Informatik, 2012
• Self-Healing Asynchronous Circuits for High-Reliability Applications / Doctoral Thesis by T. Panhofer / Supervisor, Reviewer: A. Steininger, H. Vierhaus; Institut für Technische Informatik, 2012
• Asynchronous Logic in Real-Time Systems / Doctoral Thesis by M. Ferringer / Supervisor, Reviewer: A. Steininger, G. Fohler; Institut für Technische Informatik, 2012
• Elaboration of a Fault-Tolerant Strategy for Space-born Digital Signal Processing Applications / Master Thesis by B. Fuchs / Supervisor: A. Steininger; Technische Informatik, 2012

2011

• Hardware Description with Timing Requirements / Master Thesis by S. Resch / Supervisor: A. Steininger; 191-02, 2011
• SPEAR2C - Implementing a Cache Controller into SPEAR2 / Master Thesis by M. Birner / Supervisor: A. Steininger; 191-02, 2011
• The SPEAR2 Hardware/Software Interface / Master Thesis by M. Walter / Supervisor: A. Steininger; 191-02, 2011
• Implementation of the TTP/A Protocol and WCET Analysis on the SPEAR2 Platform / Master Thesis by A. Burker / Supervisor: A. Steininger; 191-02, 2011
• Description Methods for Asynchronous Circuits - A Comparison / Master Thesis by R. Najvirt / Supervisor: A. Steininger; 191-02, 2011

2009

• Analysis of Common Cause Faults in Dual Core Architectures / Doctoral Thesis by P Tummeltshammer / Supervisor, Reviewer: A. Steininger, Z. Kotasek; Institut für Technische Informatik, 2009; oral examination: 2009-10-20
• Fault-Tolerant Distributed Algorithms for On-Chip Tick Generation: Concepts, Implementations and Evaluations / Doctoral Thesis by G. Fuchs / Supervisor, Reviewer: A. Steininger, C. Metra; Institut für Technische Informatik, 2009; oral examination: 2009-10-20
• Mapping Stereo Matching Algorithms to Hardware / Doctoral Thesis by K. Ambrosch / Supervisor, Reviewer: A. Steininger, R. Siegwart; Institut für Technische Informatik, 2009
• High-Level System Modeling with SystemC and TLM / Master Thesis by C. Widtmann / Supervisor: A. Steininger; 191-02, 2009
• Automated Regression Testing of Embedded Devices / Master Thesis by P. Jahn / Supervisor: A. Steininger, A. Reisenbauer; Institut für Technische Informatik, 2009
• Fault-Tolerant Hardware Implementation of a Consensus Algorithm / Master Thesis by T. Polzer / Supervisor: A. Steininger, T. Handl; Institut für Technische Informatik, 2009

2008

• Concepts for Virtual Prototyping of Distributed Embedded Systems / Doctoral Thesis by H. Muhr / Supervisor, Reviewer: D. Dietrich, A. Steininger; Institut für Computertechnik, 2008; oral examination: 2008-12-22
• A Transparent Online Test Approach for Time-Triggered Communication Protocols / Doctoral Thesis by E. Armengaud / Supervisor, Reviewer: A. Steininger, F. Simonot-Lion; Institut für technische Informatik, 2008
• Implementation of a Design Tool for Generation of FSL Circuits / Master Thesis by J. Lechner / Supervisor: A. Steininger; 191-02, 2008

2006

• An Asynchronous Hardware Design for Distributed Tick Generation / Master Thesis by M. Ferringer / Supervisor: A. Steininger; Technische Informatik, E182/2, 2006; final examination: 2006

2005

• Design of an Asynchronous Processor Based on Code Alternation Logic - Exploration of Delay Insensitivity / Doctoral Thesis by W. Huber / Supervisor, Reviewer: A. Steininger, R. Eier; Technische Informatik, E182/2, 2005; oral examination: 2005
• An Experimental Comparison of Robustness between Synchronous and Asynchronous Logic Design / Doctoral Thesis by B. Rahbaran / Supervisor, Reviewer: A. Steininger, R. Eier; Technische Informatik, E182/2, 2005; oral examination: 2005
• Untersuchung von fehlertoleranten Prozessorarchitekturen für sicherheitsrelevante Automobilanwendungen / Doctoral Thesis by T. Kottke / Supervisor, Reviewer: A. Steininger, H. Wunderlich; Institut für Technische Informatik, 2005
• JOP: A Java Optimized Processor for Embedded Real-Time Systems / Doctoral Thesis by M. Schöberl / Supervisor, Reviewer: A. Steininger, P. Puschner; Technische Informatik, E182, 2005; oral examination: 2005
• Design of an Asynchronous Processor Based on Code Alternation Logic - Treatment of Non-Linear Data Paths / Doctoral Thesis by M. Delvai / Supervisor, Reviewer: A. Steininger, R. Eier; Institut für Technische Informatik / Embedded Computing Systems, 2005
• Revision and Verification of an Enhanced UART / Master Thesis by R. Gallo / Supervisor: M. Delvai, A. Steininger; Technische Informatik, E182/2, 2005; final examination: 2005

2004

• A Superscalar 16 Bit Microcontroller for Real-Time Applications / Master Thesis by G. Fuchs / Supervisor: A. Steininger, M. Delvai; Institut für Technische Informatik / Embedded Computing Systems, 2004
• Multiple Constant Multiplication by Time-Multiplexed Mapping of Addition Chains / Master Thesis by P Tummeltshammer / Supervisor: A. Steininger; Institut für Technische Informatik / Embedded Computing Systems, 2004
• Implementierung eines FPGA-basierten Hardware-Fehlerinjektors / Master Thesis by T. Handl / Supervisor: A. Steininger; Institut für Technische Informatik / Embedded Computing Systems, 2004

2003

• Realisierung eines generischen Online Debuggers für Embedded Systems / Master Thesis by C. El Salloum / Supervisor: M. Delvai, A. Steininger; Institut für Technische Informatik, 2003
• Asynchrone Realisierung einer Arithmetic Logic Unit / Master Thesis by T. Pedram / Supervisor: M. Delvai, A. Steininger; Institut für Technische Informatik, 2003
• Entwicklung eines USB fullspeed VHDL-Cores / Master Thesis by M. Eggenhofer / Supervisor: J. Vilanek, A. Steininger; Institut für Technische Informatik, 2003

2002

• Zuverlässigkeit zweifach redundanter Architekturen unter besonderer Berücksichtigung latenter Fehler / Doctoral Thesis by C. Scherrer / Supervisor, Reviewer: A. Steininger, R. Patzelt; Institut für Technische Informatik, 2002
• Design and implementation of a highly efficient communication node for real-time applications / Master Thesis by U. Eisenmann / Supervisor: A. Steininger, M. Delvai; Institut für Technische Informatik, 2002
• Realization of a Re-Usable Offline Debugger for the SPEAR Micro-Controller / Master Thesis by M. Jankela / Supervisor: A. Steininger, M. Delvai; Institut für Technische Informatik, 2002
• Data Path for a FlrxRay-to-FlexRay Gateway / Master Thesis by E. Armengaud / Supervisor: A. Steininger; Institut für Technische Informatik, 2002
• Communication protocol test device in VHDL / Master Thesis by C. Resanka / Supervisor: A. Steininger; Institut für Technische Informatik, 2002

2001

• Zur Rolle der Verifikation im Designprozess digitaler integrierter Schaltungen / Doctoral Thesis by J. Vilanek / Supervisor, Reviewer: A. Steininger, R. Eier; Institut für Technische Informatik, 2001
• A Transparent Online Memory Test / Doctoral Thesis by K. Thaller / Supervisor, Reviewer: A. Steininger, R. Eier; Institut für Technische Informatik, 2001

2000

• Entwicklung eines Mikrokontrollers für das Echtzeitprotokoll TTP/A / Master Thesis by M. Delvai / Supervisor: A. Steininger, W. Elmenreich; Institut für Technische Informatik, 2000
• Simulation einer SCSI-Festplatte unter LINUX / Master Thesis by W. Huber / Supervisor: A. Steininger; Institut für Technische Informatik, 2000
• Entwicklung eines Mikroprozessorsmit Built-in Self-Test / Master Thesis by T. Hinterstoisser / Supervisor: A. Steininger; Institut für Technische Informatik, 2000
• Experimentelle Verifikation eines Transparent Online Memory Test / Master Thesis by R. Steinwendtner / Supervisor: A. Steininger; Institut für Technische Informatik, 2000