TU Wien Informatics

Andreas Steininger

Ao.Univ.Prof. Dipl.-Ing. Dr.techn.

Research Focus

Research Areas

  • Timing domain interfacing, Clockless Processors, Dependable Computer Systems, Error Detection Mechanisms, Fault Tolerance, Computer Architecture, Built in Self Test (BIST)
Andreas Steininger

About

Asynchronous Logic, Fault Tolerant Clocking, Timing Domain Interfacing (Metastability), Fault Tolerant Architectures, Radiation Effects in Micorelectronics

Roles

2021

2020

  • On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective / R. El Shahaby, A. Steininger / Talk: IEEE International Conference on Computer Design, Hartford, Connecticut, USA; 2020-10-18 - 2020-10-21; in: "Proceedings IEEE International Conference on Computer Design", (2020), 1 - 4
  • Sorting Network based Full Adders for QDI Circuits / F. Huemer, A. Steininger / Talk: 28th Austrian Workshop on Microelectronics, Wien; 2020-10-07; in: "Proceedings 28th Austrian Workshop on Microelectronics", (2020), 1 - 8
  • Identification and Confinement of Fault Sensitivity Windows in QDI Logic / F. Huemer, R. Najvirt, A. Steininger / Talk: 28th Austrian Workshop on Microelectronics, Wien; 2020-10-07; in: "Proceedings 28th Austrian Workshop on Microelectronics", (2020), 1 - 8
  • Timing Domain Crossing using Muller Pipelines / F. Huemer, A. Steininger / Talk: 26th IEEE International Symposium on Asynchronous Circuits and Systems, Snowbird, Utah, USA; 2020-05-17 - 2020-05-20; in: "Proceedings 26th IEEE International Symposium on Asynchronous Circuits and Systems", Ieee Cs, (2020), ISSN: 2643-1483; 1 - 10
  • Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock / W. Dür, A. Steininger / Talk: 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Novi Sad; 2020-04-22 - 2020-04-24; in: "Proceedings 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", Ieee Cs, (2020), 1 - 6
  • Welcome Message: ASYNC 2020 / E. Brunvand, K. Stevens, M. Moreira, A. Steininger / in: "Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)", IEEE Computer Society, 2020, (invited), ISBN: 978-1-7281-5495-4, 2 pages

2019

2018

2017

2016

  • A Programmable Delay Line for Metastability Characterization in FPGAs / T. Polzer, F. Huemer, A. Steininger / Talk: 24th Austrian Workshop on Microelectronics (Austrochip), Villach; 2016-10-19; in: "Proceedings 24th Austrian Workshop on Microelectronics", (2016), 6 pages
  • A New Coding Scheme for Fault Tolerant 4-Phase Delay-Insensitive Codes / F. Huemer, J. Lechner, A. Steininger / Poster: 2016 IEEE International Conference on Computer Design, Phoenix, Arizona, USA; 2016-10-03 - 2016-10-05; in: "Proceedings 2016 IEEE International Conference on Computer Design", (2016), ISBN: 978-1-5090-5142-7; 392 - 395
  • Design and Physical Implementation of a Target ASIC for SET Experiments / V. S. Veeravalli, A. Steininger / Poster: 2016 Euromicro Conference on Digital System Design (DSD), Limassol, Portugal; 2016-08-31 - 2016-09-02; in: "Proc. 2016 Euromicro Conference on Digital System Design (DSD)", IEEE, (2016), ISBN: 978-1-5090-2817-7; 694 - 697
  • Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? / A. Steininger, R. Najvirt, J. Maier / Talk: 2016 Euromicro Conference on Digital System Design (DSD), Limassol, Portugal; 2016-08-31 - 2016-09-02; in: "2016 Euromicro Conference on Digital System Design (DSD)", IEEE, (2016), ISBN: 978-1-5090-2817-7; 372 - 379
  • Study of a Delayed Single-Event Effect in the Muller C-element / V. S. Veeravalli, A. Steininger / Poster: 21st IEEE European Test Symposium, Amsterdam; 2016-05-24 - 2016-05-27; in: "Proc 21st IEEE European Test Symposium", (2016), ISBN: 978-1-4673-9659-2
  • The Metastable Behavior of a Schmitt-Trigger / A. Steininger, J. Maier, R. Najvirt / Talk: 22nd IEEE International Symposium on Asynchronous Circuits and Systems, Porto Alegre -- Brazil; 2016-05-08 - 2016-05-11; in: "2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)", IEEE Computer Society Conference Publishing Services (CPS), (2016), ISBN: 978-1-4673-9007-1; 57 - 64
  • A General Approach for Comparing Metastable Behavior of Digital CMOS Gates / T. Polzer, A. Steininger / Talk: 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Kosice, Slovakia; 2016-04-20 - 2016-04-22; in: "Proc 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2016), ISBN: 978-1-5090-2467-4; 6 pages
  • Fifty Shades of Synchrony / A. Steininger / in: "This Asynchronous Woirld", A. Mokhov (ed.); Newcastle University, Newcastle upon Tyne, 2016, (invited), ISBN: 978-0-7017-0257-1, 294 - 300

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1995

  • The Implementation of the MARS Hardware and Software / J. Reisinger, A. Steininger, G. Leber / in: "Predicatbly Dependable Computing Systems", B. Randell, J. Laprie, H. Kopetz, B. Littlewood (ed.); issued by: ESPRIT Basic Research Series; Springer International Publishing, 1995, ISBN: 3-540-59334-9, 209 - 224

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