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Andreas Steininger

Ao.Univ.Prof. Dipl.-Ing. Dr.techn.

Research Focus

  • Computer Engineering: 100%

Research Areas

  • Timing domain interfacing, Clockless Processors, Dependable Computer Systems, Error Detection Mechanisms, Fault Tolerance, Computer Architecture, Built in Self Test (BIST)
Andreas Steininger

About

Asynchronous Logic, Fault Tolerant Clocking, Timing Domain Interfacing (Metastability), Fault Tolerant Architectures, Radiation Effects in Micorelectronics

Roles

  • Associate Professor
    Embedded Computing Systems, E191-02
  • Doctoral School
    Director
  • Faculty Council
    Substitute Member
  • Curriculum Commission for Computer Engineering
    Principal Member

Contact

2023W

 

2022

2021

  • Generation of a fault-tolerant clock through redundant crystal oscillators / Dür, W., Függer, M., & Steininger, A. (2021). Generation of a fault-tolerant clock through redundant crystal oscillators. Microelectronics Reliability, 120, 1–11. https://doi.org/10.1016/j.microrel.2021.114088
    Download: PDF (1.46 MB)
  • Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles / Behal, P., Huemer, F., Najvirt, R., Tabassam, Z., & Steininger, A. (2021). Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. In 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 27th IEEE International Symposium on Asynchronous Circuits and Systems, online, Austria. https://doi.org/10.34726/3945
    Download: PDF (717 KB)
  • Input/Output-Interlocking for Fault Mitigation in QDI Pipelines / Tabassam, Z., Behal, P., Najvirt, R., & Steininger, A. (2021). Input/Output-Interlocking for Fault Mitigation in QDI Pipelines. In 2021 Austrochip Workshop on Microelectronics (Austrochip) (pp. 17–20). https://doi.org/10.34726/3943
    Download: PDF (267 KB)
  • Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines / Elshehaby, R., & Steininger, A. (2021). Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Wien, Austria. Ieee Cs. https://doi.org/10.34726/4046
    Download: PDF (497 KB)
  • An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits / Behal, P., Huemer, F. F., Najvirt, R., & Steininger, A. (2021). An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. In 2021 24th Euromicro Conference on Digital System Design (DSD). 24th Euromicro Conference on Digital System Design, Palermo, Italy, EU. https://doi.org/10.34726/4044
    Download: PDF (506 KB)
  • Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles / Behal, P., Huemer, F., Najvirt, R., Steininger, A., & Tabassam, Z. (2021). Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). https://doi.org/10.1109/async48570.2021.00012
  • Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses / Maier, J., Hartl-Nesic, C., & Steininger, A. (2021). Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(3), 1013–1026. https://doi.org/10.1109/tcsi.2021.3130349
  • Generation of a fault-tolerant clock through redundant crystal oscillators / Dür, W., Függer, M., & Steininger, A. (2021). Generation of a fault-tolerant clock through redundant crystal oscillators. Microelectronics Reliability, 120(114088), 114088. https://doi.org/10.1016/j.microrel.2021.114088
  • Foreword / Sekanina, L., Shafique, M., Krstic, M., Steininger, A., & Stojanovic, G. (2021). Foreword. In 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE. https://doi.org/10.1109/ddecs52668.2021.9417019

2020

  • Identification and Confinement of Fault Sensitivity Windows in QDI Logic / Huemer, F. F., Najvirt, R., & Steininger, A. (2020). Identification and Confinement of Fault Sensitivity Windows in QDI Logic. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. https://doi.org/10.34726/4043
    Download: PDF (1.76 MB)
  • Timing Domain Crossing using Muller Pipelines / Huemer, F. F., & Steininger, A. (2020). Timing Domain Crossing using Muller Pipelines. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 26th IEEE International Symposium on Asynchronous Circuits and Systems, Snowbird, Utah, USA, Austria. Ieee Cs. https://doi.org/10.34726/4041
    Download: PDF (330 KB)
  • On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective / Elshehaby, R., & Steininger, A. (2020). On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. In 2020 IEEE 38th International Conference on Computer Design (ICCD). IEEE International Conference on Computer Design, Hartford, Connecticut, USA, Austria. https://doi.org/10.34726/4045
    Download: PDF (462 KB)
  • Sorting Network based Full Adders for QDI Circuits / Huemer, F. F., & Steininger, A. (2020). Sorting Network based Full Adders for QDI Circuits. In 2020 Austrochip Workshop on Microelectronics (Austrochip). 28th Austrian Workshop on Microelectronics, Wien, Austria. https://doi.org/10.34726/4042
    Download: PDF (280 KB)
  • Welcome Message: ASYNC 2020 / Brunvand, E., Stevens, K., Moreira, M., & Steininger, A. (2020). Welcome Message: ASYNC 2020. In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE Computer Society. https://doi.org/10.1109/async49171.2020.00005
  • Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock / Duer, W., & Steininger, A. (2020). Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock. In 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Novi Sad, EU. Ieee Cs. https://doi.org/10.1109/ddecs50862.2020.9095577

2019

2018

  • Refined Metastability Characterization Using a Time-to-Digital Converter / Polzer, T., Huemer, F., & Steininger, A. (2018). Refined Metastability Characterization Using a Time-to-Digital Converter. Microelectronics Reliability, 80, 91–99. https://doi.org/10.1016/j.microrel.2017.11.017
  • Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA / Huemer, F., Polzer, T., & Steininger, A. (2018). Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. In 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/ddecs.2018.00032
  • State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration / Schütz, M., Steininger, A., Huemer, F., & Lechner, J. (2018). State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/dft.2018.8602984
    Project: Intel CARS (2017–2019)
  • Advanced Delay-Insensitive 4-Phase Protocols / Huemer, F., & Steininger, A. (2018). Advanced Delay-Insensitive 4-Phase Protocols. In 2018 Austrochip Workshop on Microelectronics (Austrochip). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/austrochip.2018.8520702
  • Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication / Huemer, F., & Steininger, A. (2018). Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. In 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE CS Press, Austria. IEEE Xplore Digital Library. https://doi.org/10.1109/async.2018.00014

2017

  • Novel Trends in Design & Test / Steininger, A., Pawlak, A., & Stopjakova, V. (2017). Novel Trends in Design & Test. Journal of Circuits, Systems, and Computers, 26(08), 1702001. https://doi.org/10.1142/s0218126617020017
  • A Model for the Metastability Delay of Sequential Elements / Polzer, T., & Steininger, A. (2017). A Model for the Metastability Delay of Sequential Elements. Journal of Circuits, Systems, and Computers, 26(08), 1740010. https://doi.org/10.1142/s0218126617400102
  • A versatile architecture for long-term monitoring of single-event transient durations / Savulimedu Veeravalli, V., Steininger, A., & Schmid, U. (2017). A versatile architecture for long-term monitoring of single-event transient durations. Microprocessors and Microsystems, 53, 130–144. https://doi.org/10.1016/j.micpro.2017.07.007
  • Setup for an Experimental Study of Radiation Effects in 65nm CMOS / Fritz, B., Veeravalli, V. S., Steininger, A., & Simek, V. (2017). Setup for an Experimental Study of Radiation Effects in 65nm CMOS. In 2017 Euromicro Conference on Digital System Design (DSD). 20th Euromicro Conference on Digital System Design, Wien, Austria. https://doi.org/10.1109/dsd.2017.60
  • A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study / Andjelkovic, M., Krstic, M., Kraemer, R., Veeravalli, V. S., & Steininger, A. (2017). A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. In Proceedings of the 26th IEEE Asian Test Symposium (ATS´17) (pp. 1–6). http://hdl.handle.net/20.500.12708/57265
  • Measuring metastability using a time-to-digital converter / Polzer, T., Huemer, F., & Steininger, A. (2017). Measuring metastability using a time-to-digital converter. In 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Dresden, EU. IEEE Service Center. https://doi.org/10.1109/ddecs.2017.7934582
  • Measuring Metastability with Free-Running Clocks / Najvirt, R., Polzer, T., & Steininger, A. (2017). Measuring Metastability with Free-Running Clocks. In 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California, Non-EU. IEEE Computer Society. https://doi.org/10.1109/async.2017.18

2016

2015

2014

  • Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic / Maier, J., & Steininger, A. (2014). Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic. In 17th International Symposium on Design and Diagnostics of Electronic Circuits Systems / Pleskacz, Witold; Renovell, Michel; Kasprowicz, Dominik; Sekanina, Lukáš; Bernard, Serge. Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/DDECS.2014.6868759
    Download: PDF (266 KB)
  • Runtime verification of microcontroller binary code / Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., & Kowalewski, S. (2014). Runtime verification of microcontroller binary code. Science of Computer Programming, 80, 109–129. https://doi.org/10.1016/j.scico.2012.10.015
  • Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip / Dolev, D., Függer, M., Posch, M., Schmid, U., Steininger, A., & Lenzen, C. (2014). Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip. Journal of Computer and System Sciences, 80(4), 860–900. https://doi.org/10.1016/j.jcss.2014.01.001
  • Equivalence of clock gating and synchronization with applicability to GALS communication / Najvirt, R., & Steininger, A. (2014). Equivalence of clock gating and synchronization with applicability to GALS communication. In 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, Isles Balears, Spain, EU. IEEE. https://doi.org/10.1109/patmos.2014.6951873
  • Long term on-chip monitoring of SET pulsewidths in a fully digital ASIC / Veeravalli, V. S., & Steininger, A. (2014). Long term on-chip monitoring of SET pulsewidths in a fully digital ASIC. In 22nd Austrian Workshop on Microelectronics (Austrochip). 22nd Austrian Workshop on Microelectronics, Graz, Austria. IEEE. https://doi.org/10.1109/austrochip.2014.6946318
    Project: EASET (2014–2017)
  • Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example / Steininger, A., Veeravalli, V. S., Alexandrescu, D., Costenaro, E., & Anghel, L. (2014). Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. In 2014 IEEE 32nd International Conference on Computer Design (ICCD). 2014 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea, Non-EU. IEEE. https://doi.org/10.1109/iccd.2014.6974663
    Project: EASET (2014–2017)
  • A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments / Naqvi, S. R., & Steininger, A. (2014). A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments. In Proceedings Design Automation &Test in Europe (p. 6). http://hdl.handle.net/20.500.12708/55132
  • Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum / Anghel, L., Veeravalli, V. S., Alexandrescu, D., Steininger, A., Schneider, K., & Costenaro, E. (2014). Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum. In Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10) (p. 6). http://hdl.handle.net/20.500.12708/55131
  • Diagnosis of SET Propagation in Combinational Logic under Dynamic Operation / Veeravalli, V. S., & Steininger, A. (2014). Diagnosis of SET Propagation in Combinational Logic under Dynamic Operation. In Proceedings 2014 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 10) (p. 6). http://hdl.handle.net/20.500.12708/55130
  • Architecture for monitoring SET propagation in 16-bit Sklansky adder / Veeravalli, V. S., & Steininger, A. (2014). Architecture for monitoring SET propagation in 16-bit Sklansky adder. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA, Non-EU. https://doi.org/10.1109/isqed.2014.6783354
  • Measuring SET pulsewidths in logic gates using digital infrastructure / Veeravalli, V. S., Steininger, A., & Schmid, U. (2014). Measuring SET pulsewidths in logic gates using digital infrastructure. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA, Non-EU. https://doi.org/10.1109/isqed.2014.6783331
  • Protection of Muller-Pipelines from transient faults / Naqvi, S. R., Lechner, J., & Steininger, A. (2014). Protection of Muller-Pipelines from transient faults. In Fifteenth International Symposium on Quality Electronic Design. 15th International Symposium & Exhibit on Quality Electronic Design, Santa Clara, USA, Non-EU. https://doi.org/10.1109/isqed.2014.6783315

2013

2012

2011

  • Replicated processors on a single die - How independently do they fail? / Steininger, A., & Tummeltshammer, P. (2011). Replicated processors on a single die - How independently do they fail? Elektrotechnik Und Informationstechnik : E & i, 128(6), 245–250. https://doi.org/10.1007/s00502-011-0005-9
  • VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation / Fuchs, G., & Steininger, A. (2011). VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation. Canadian Journal of Electrical and Computer Engineering, 2011. https://doi.org/10.1155/2011/936712
    Project: DARTS (2005–2010)
  • Hardware support for efficient testing of embedded software / Reinbacher, T., Steininger, A., Müller, T., Horauer, M., Brauer, J., & Kowalewski, S. (2011). Hardware support for efficient testing of embedded software. In International Conference on Mechatronic and Embedded Systems and Applications. The 7th ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications, Washington, Non-EU. ASME. http://hdl.handle.net/20.500.12708/54082
    Project: CEVTES (2010–2013)
  • Automated test-trace inspection for microcontroller binary code / Reinbacher, T., Brauer, J., Schachinger, D., Steininger, A., & Kowalewski, S. (2011). Automated test-trace inspection for microcontroller binary code. In Runtime Verification (pp. 239–244). http://hdl.handle.net/20.500.12708/54078
    Project: CEVTES (2010–2013)
  • Past Time LTL Runtime Verification for Microcontroller Binary Code / Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., & Kowalewski, S. (2011). Past Time LTL Runtime Verification for Microcontroller Binary Code. In Formal Methods for Industrial Critical Systems (pp. 37–51). Springer Berlin / Heidelberg. https://doi.org/10.1007/978-3-642-24431-5_5
    Project: CEVTES (2010–2013)

2010

  • Test-Case Generation for Embedded Binary Code Using Abstract Interpretation / Reinbacher, T., Brauer, J., Horauer, M., Steininger, A., & Kowalewski, S. (2010). Test-Case Generation for Embedded Binary Code Using Abstract Interpretation. In MEMICS proceedings (pp. 151–158). http://hdl.handle.net/20.500.12708/53554
    Project: CEVTES (2010–2013)
  • Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study. In 2010 NASA/ESA Conference on Adaptive Hardware and Systems. NASA/ESA 2010 (Conference on Adaptive Hardware and Systems), Anaheim, CA, USA, Non-EU. IEEE Computer Society. https://doi.org/10.1109/ahs.2010.5546277
  • Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm. In 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W). WSDN 2010 (4th Workshop on Dependable and Secure Nanocomputing, Chicago, IL, USA, Non-EU. IEEE Computer Socitey. https://doi.org/10.1109/dsnw.2010.5542609
  • A deterministic approach for hardware fault injection in asynchronous QDI logic / Friesenbichler, W., Panhofer, T., & Steininger, A. (2010). A deterministic approach for hardware fault injection in asynchronous QDI logic. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE. https://doi.org/10.1109/ddecs.2010.5491758
  • Enhancing pipelined processor architectures with fast autonomous recovery of transient faults / Jeitler, M., Lechner, J., & Steininger, A. (2010). Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. In 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2010 (Design and Diagnostics of Electronic Circuits and Systems), Vienna, Austria, Austria. IEEE Computer Society. https://doi.org/10.1109/ddecs.2010.5491776

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