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Peter Puschner

Ao.Univ.Prof. Dipl.-Ing. Dr.techn.

Research Focus

  • Computer Engineering: 80%
  • Information Systems Engineering: 20%

Research Areas

  • Worst-Case Execution Time Analysis and Timing Analysis, SW/HW Architectures for Real-Time Systems, Real-Time Systems, Embedded Systems, Software Testing
Peter Puschner

About

Peter Puschner is Professor for Computer Engineering and Faculty Representative (responsible for research and infrastructure) at the Faculty of Informatics. His research focus is on the timing analysis of real-time computer systems and the design of time-predictable hardware and software architectures for safety-critical real-time systems.

Roles

Contact

2024W

2025S

 

2024

  • Predictable and optimized single-path code for predicated processors / Maroun, E. J., Schoeberl, M., & Puschner, P. (2024). Predictable and optimized single-path code for predicated processors. Journal of Systems Architecture, 154, Article 103214. https://doi.org/10.1016/j.sysarc.2024.103214
  • The Platin Multi-Target Worst-Case Analysis Tool / Maroun, E. J., Dengler, E., Dietrich, C., Hepp, S., Herzog, H., Huber, B., Knoop, J., Wiltsche-Prokesch, D., Puschner, P., Raffeck, P., Schoeberl, M., Schuster, S., & Wägemann, P. (2024). The Platin Multi-Target Worst-Case Analysis Tool. In T. Carle (Ed.), 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024) (pp. 2:1-2:14). Schloss Dagstuhl. https://doi.org/10.4230/OASIcs.WCET.2024.2
  • Two-Step Register Allocation for Implementing Single-Path Code / Maroun, E. J., Schoeberl, M., & Puschner, P. (2024). Two-Step Register Allocation for Implementing Single-Path Code. In 2024 IEEE 27th International Symposium on Real-Time Distributed Computing (ISORC) (pp. 1–12). IEEE. https://doi.org/10.1109/ISORC61049.2024.10551362

2023

  • Compiler-Directed Constant Execution Time on Flat Memory Systems / Maroun, E. J., Schoeberl, M., & Puschner, P. (2023). Compiler-Directed Constant Execution Time on Flat Memory Systems. In M. Ashjaei, A. Gokhale, & N. Guan (Eds.), 2023 IEEE 26th International Symposium on Real-Time Distributed Computing (ISORC) (pp. 64–75). IEEE. https://doi.org/10.1109/ISORC58943.2023.00019
  • Constant-Loop Dominators for Single-Path Code Optimization / Maroun, E. J., Schoeberl, M., & Puschner, P. (2023). Constant-Loop Dominators for Single-Path Code Optimization. In P. Wägemann (Ed.), 21th International Workshop on Worst-Case Execution Time Analysis (WCET 2023) (pp. 1–13). Schloss-Dagstuhl - Leibniz Zentrum für Informatik. https://doi.org/10.4230/OASIcs.WCET.2023.7
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  • A qualitative cybersecurity analysis of time-triggered communication networks in automotive systems / Kirner, R., & Puschner, P. (2023). A qualitative cybersecurity analysis of time-triggered communication networks in automotive systems. Journal of Systems Architecture, 136, Article 102835. https://doi.org/10.1016/j.sysarc.2023.102835

2022

2021

2020

  • Synchronizing Real-Time Tasks in Time-Aware Networks: Work-in-Progress / Kyriakakis, E., Sparso, J., Puschner, P., & Schoeberl, M. (2020). Synchronizing Real-Time Tasks in Time-Aware Networks: Work-in-Progress. In 2020 International Conference on Embedded Software (EMSOFT). 2020 International Conference on Embedded Software (EMSOFT), Singapur, Singapore. ACM. https://doi.org/10.1109/emsoft51651.2020.9244029
  • An Instruction Filter for Time-Predictable Code Execution on Standard Processors / Platzer, M., & Puschner, P. (2020). An Instruction Filter for Time-Predictable Code Execution on Standard Processors. In Springer Verlag (Ed.), Computer Safety, Reliability, and Security. SAFECOMP 2020 Workshops (pp. 111–122). Springer. https://doi.org/10.1007/978-3-030-55583-2_8
  • Towards Dual-Issue Single-Path Code / Maroun, E. J., Schoeberl, M., & Puschner, P. (2020). Towards Dual-Issue Single-Path Code. In 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC). 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC), Nashville, United States of America (the). https://doi.org/10.1109/isorc49007.2020.00039
  • A Real-Time Application with Fully Predictable Task Timing / Platzer, M., & Puschner, P. (2020). A Real-Time Application with Fully Predictable Task Timing. In 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC). 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC), Nashville, United States of America (the). https://doi.org/10.1109/isorc49007.2020.00016
  • Asynchronous vs. synchronous interfacing to time-triggered communication systems / Puschner, P., & Kirner, R. (2020). Asynchronous vs. synchronous interfacing to time-triggered communication systems. The Journal of Systems Architecture: Embedded Software Design, 103(101690), 101690. https://doi.org/10.1016/j.sysarc.2019.101690

2019

  • Composable Component Interfaces for Time-Triggered Systems / Puschner, P., & Frömel, B. (2019). Composable Component Interfaces for Time-Triggered Systems. In 2019 8th Mediterranean Conference on Embedded Computing (MECO). 8th Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro. IEEE. https://doi.org/10.1109/meco.2019.8760059
  • Interfacing to Time-Triggered Communication Systems / Puschner, P., & Kirner, R. (2019). Interfacing to Time-Triggered Communication Systems. In 2019 IEEE 22nd International Symposium on Real-Time Distributed Computing (ISORC). IEEE 22nd International Symposium on Real-Time Distributed Computing (ISORC), Valencia, Spain. IEEE. https://doi.org/10.1109/isorc.2019.00044

2017

  • Error detection based on execution-time monitoring / Steiner, D., & Puschner, P. (2017). Error detection based on execution-time monitoring. In 2017 6th Mediterranean Conference on Embedded Computing (MECO). 6th Mediterranean Conference on Embedded Computing (MECO), Bar, Montenegro. IEEE. https://doi.org/10.1109/meco.2017.7977166
  • Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy / Cilku, B., Puffitsch, W., Prokesch, D., Schoeberl, M., & Puschner, P. (2017). Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy. In 2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC). 20th IEEE International Symposium on Real-Time Computing (ISORC 2017), Toronto, Canada. IEEE. https://doi.org/10.1109/isorc.2017.17
  • Best Practice for Caching of Single-Path Code / Schoeberl, M., Cilku, B., Prokesch, D., & Puschner, P. (2017). Best Practice for Caching of Single-Path Code. In J. Reineke (Ed.), 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017) (pp. 2:1-2:12). Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/OASIcs.WCET.2017.2

2016

  • Composable Component Interfaces for Time-Triggered Systems / Puschner, P., & Frömel, B. (2016). Composable Component Interfaces for Time-Triggered Systems. In Proc. 19th IEEE International Symposium on Real-Time Computing (ISORC 2016) Workshops. 12th International IEEE/IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2016), York, United Kingdom of Great Britain and Northern Ireland (the). http://hdl.handle.net/20.500.12708/56731
  • Constructing Time-Predictable MPSoCs: Avoid Conflicts in Temporal Control / Puschner, P., Cilku, B., & Prokesch, D. (2016). Constructing Time-Predictable MPSoCs: Avoid Conflicts in Temporal Control. In 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC). IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Lyon, France. 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems on Chip; ISBN 978-1-5090-3530-4. https://doi.org/10.1109/mcsoc.2016.55
  • Semi-formal Representation of Requirements for Automotive Solutions Using SysML / Muşat, L., Hübl, M., Buzo, A., Pelz, G., Kandl, S., & Puschner, P. (2016). Semi-formal Representation of Requirements for Automotive Solutions Using SysML. In Languages, Design Methods, and Tools for Electronic System Design (pp. 57–81). Springer International Publishing. https://doi.org/10.1007/978-3-319-24457-0_4

2015

  • Requirement Semi-formalization Methodology for SoC Design (Best Paper Award) / Musat, L., Kandl, S., Puschner, P., Hübl, M., Buzo, A., & Pelz, G. (2015). Requirement Semi-formalization Methodology for SoC Design (Best Paper Award). In Proceedings of the 12th International SoC Design Conference (IEEE). 12th International SoC Design Conference (ISOCC 2015), Gyeongju, Korea (the Republic of). http://hdl.handle.net/20.500.12708/56242
  • A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking / Cilku, B., Prokesch, D., & Puschner, P. (2015). A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking. In 2015 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops. 11th International IEEE/IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems SEUS 2015, Auckland, New Zealand. IEEE. https://doi.org/10.1109/isorcw.2015.58
  • A Generator for Time-Predictable Code / Prokesch, D., Hepp, S., & Puschner, P. (2015). A Generator for Time-Predictable Code. In 2015 IEEE 18th International Symposium on Real-Time Distributed Computing. 18th IEEE International Symposium on Real-Time Computing (ISORC 2015), Auckland, New Zealand. IEEE. https://doi.org/10.1109/isorc.2015.40
  • A TDMA-Based arbitration scheme for mixed-criticality multicore platforms / Cilku, B., Crespo, A., Puschner, P., Coronel, J., & Salvador, P. (2015). A TDMA-Based arbitration scheme for mixed-criticality multicore platforms. In 2015 International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP). The first international conference on Event-based Control, Communication, and Signal Processing (EBCCSP), 2015, Krakow, Poland. IEEE. https://doi.org/10.1109/ebccsp.2015.7300671
  • The platin Tool Kit - The T-CREST Approach for Compiler and WCET Integration / Hepp, S., Huber, B., Knoop, J., Prokesch, D., & Puschner, P. (2015). The platin Tool Kit - The T-CREST Approach for Compiler and WCET Integration. In 18. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS) 2015. 18. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS) 2015, Pörtschach am Wörthersee, Austria. http://hdl.handle.net/20.500.12708/56394
  • A Strategy for Generating Time-Predictable Code / Prokesch, D., & Puschner, P. (2015). A Strategy for Generating Time-Predictable Code. In 18. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS) 2015. 18. Kolloquium Programmiersprachen und Grundlagen der Programmierung (KPS) 2015, Pörtschach am Wörthersee, Austria. http://hdl.handle.net/20.500.12708/56375
  • T-CREST: Time-Predictable Multi-Core Architecture for Embedded Systems / Schoeberl, M., Abbaspour, S., Akesson, B., Audsley, N., Capasso, R., Garside, J., Goossens, K., Goossens, S., Hansen, S., Heckmann, R., Hepp, S., Huber, B., Jordan, A., Kasapaki, E., Knoop, J., Li, Y., Prokesch, D., Puffitsch, W., Puschner, P., … Tocchi, A. (2015). T-CREST: Time-Predictable Multi-Core Architecture for Embedded Systems. Journal of Systems Architecture, 61(9), 449–471. https://doi.org/10.1016/j.sysarc.2015.04.002

2014

  • Semi-formal Representation of Requirements for Automotive Solutions using SysML / Musat, L., Hübl, M., Buzo, A., Pelz, G., Kandl, S., & Puschner, P. (2014). Semi-formal Representation of Requirements for Automotive Solutions using SysML. In Proceedings of the Forum on Specification & Design Languages (FDL 2014). Forum on specification & Design Languages (FDL), Southampton, UK, EU. http://hdl.handle.net/20.500.12708/55272
  • Towards Automated Generation of Time-Predictable Code / Prokesch, D., Huber, B., & Puschner, P. (2014). Towards Automated Generation of Time-Predictable Code. In H. Falk (Ed.), 14th International Workshop on Worst-Case Execution Time Analysis (pp. 103–112). Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/OASIcs.WCET.2014.103
  • Formal Verification at System Level / Kandl, S., Elshuber, M., & Puschner, P. (2014). Formal Verification at System Level. HiPEAC 2014 (International Conference on High-Performance and Embedded Architectures and Compilers), Vienna, Austria. http://hdl.handle.net/20.500.12708/85778
  • A Novel Modeling Framework for Time-Triggered Safety-Critical Embedded Systems / Ayestaran, I., Nicolas, C. F., Perez, J., Ortube, A. L., & Puschner, P. (2014). A Novel Modeling Framework for Time-Triggered Safety-Critical Embedded Systems. In Proceedings of the Forum on Specification & Design Languages (FDL 2014). Forum on specification & Design Languages (FDL), Southampton, UK, EU. http://hdl.handle.net/20.500.12708/55769
  • A Memory Arbitration Scheme for Mixed-Criticality Multicore Platforms / Cilku, B., & Puschner, P. (2014). A Memory Arbitration Scheme for Mixed-Criticality Multicore Platforms. In Proceedings of the 2 nd International Workshop on Mixed Criticality Systems (pp. 27–32). http://hdl.handle.net/20.500.12708/55767
  • Designing a Time-Predictable Memory Hierarchy for Single-Path Code / Cilku, B., & Puschner, P. (2014). Designing a Time-Predictable Memory Hierarchy for Single-Path Code. In Designing a Time-Predictable Memory Hierarchy for Single-Path Code (pp. 9–14). http://hdl.handle.net/20.500.12708/55766
  • A Dual-Layer Bus Arbiter for Mixed-Criticality Systems with Hypervisors / Cilku, B., Frömel, B., & Puschner, P. (2014). A Dual-Layer Bus Arbiter for Mixed-Criticality Systems with Hypervisors. In Proc. of the 12th IEEE International Conference on Industrial Informatics (pp. 147–151). http://hdl.handle.net/20.500.12708/55765
  • Modeling and Simulated Fault Injection for Time-Triggered Safety-Critical Embedded Systems / Ayestaran, I., Nicolas, C. F., Perez, J., Ortube, A. L., & Puschner, P. (2014). Modeling and Simulated Fault Injection for Time-Triggered Safety-Critical Embedded Systems. In Proceedings 17th IEEE Symposium on Object/Component/Service-oriented Real-time distributed Computing (ISORC) (pp. 180–187). IEEE. http://hdl.handle.net/20.500.12708/55782
  • Security Application of Failure Mode and Effect Analysis (FMEA) / Schmittner, C., Gruber, T., Puschner, P., & Schoitsch, E. (2014). Security Application of Failure Mode and Effect Analysis (FMEA). In Computer Safety, Reliability and Security (pp. 310–325). Lecture Notes in Computer Science / Springer. http://hdl.handle.net/20.500.12708/55780
  • A Simulated Fault Injection Framework for Time-Triggered Safety-Critical Embedded Systems / Ayestaran, I., Nicolas, C. F., Perez, J., Ortube, A. L., & Puschner, P. (2014). A Simulated Fault Injection Framework for Time-Triggered Safety-Critical Embedded Systems. In Computer Safety, Reliability and Security (pp. 1–16). Lecture Notes in Computer Science / Springer. http://hdl.handle.net/20.500.12708/55779
  • Modeling logical execution time based safety-critical embedded systems in SystemC / Ayestaran, I., Nicolas, C. F., Perez, J., & Puschner, P. (2014). Modeling logical execution time based safety-critical embedded systems in SystemC. In 2014 3rd Mediterranean Conference on Embedded Computing (MECO). The Third Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro, Non-EU. IEEE. https://doi.org/10.1109/meco.2014.6862662

2013

  • Improving System-Level Verification of SystemC Models with SPIN / Elshuber, M., Kandl, S., & Puschner, P. (2013). Improving System-Level Verification of SystemC Models with SPIN. In C. Choppy & J. Sun (Eds.), 1st French Singaporean Workshop on Formal Methods and Applications (pp. 74–79). Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/OASIcs.FSFMA.2013.74
  • The platin Toolkit: A Core Component of the T-CREST Approach for Compiler and WCET-Analysis Integration / Puschner, P., Prokesch, D., Huber, B., Knoop, J., Hepp, S., & Gebhard, G. (2013). The platin Toolkit: A Core Component of the T-CREST Approach for Compiler and WCET-Analysis Integration. July’13 Meeting of the EU FP7 Cost Action no. IC1202 Timing Analysis on Code-Level (TACLe)", Paris, EU. http://hdl.handle.net/20.500.12708/85575
  • Aligning Single Path Loops to Reduce the Number of Capacity Cache Misses / Cilku, B., Kammerer, R., & Puschner, P. (2013). Aligning Single Path Loops to Reduce the Number of Capacity Cache Misses. In Proceedings of the 34th IEEE Real-Time Systems Symposium, 6th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems. 6th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems, Vancouver, Canada, Non-EU. http://hdl.handle.net/20.500.12708/54805
  • Towards Temporal and Spatial Isolation in Memory Hierarchies for Mixed-Criticality Systems with Hypervisors / Cilku, B., & Puschner, P. (2013). Towards Temporal and Spatial Isolation in Memory Hierarchies for Mixed-Criticality Systems with Hypervisors. In Proceedings of the 19th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 1st workshop on Real-Time Mixed Criticality Systems. 1st Workshop on Real-Time Mixed Criticality Systems, Taipei, Taiwan, Non-EU. http://hdl.handle.net/20.500.12708/54804
  • Combined WCET analysis of bitcode and machine code using control-flow relation graphs / Huber, B., Prokesch, D., & Puschner, P. (2013). Combined WCET analysis of bitcode and machine code using control-flow relation graphs. In ACM SIGPLAN Notices (pp. 163–172). The Association for Computing Machinery. https://doi.org/10.1145/2499369.2465567
  • Constructing Time-Critical Embedded Systems: Decide Before Runtime / Puschner, P. (2013). Constructing Time-Critical Embedded Systems: Decide Before Runtime. In Proceedings 2nd Mediterranean Conference on Embedded Computing (MECO) (p. 3). IEEE. http://hdl.handle.net/20.500.12708/55778
  • Embedded Systems for Safety-Critical and Mixed-Criticality Applications / Puschner, P. (2013). Embedded Systems for Safety-Critical and Mixed-Criticality Applications. In Proceedings 2nd Mediterranean Conference on Embedded Computing (MECO) (p. 15). IEEE. http://hdl.handle.net/20.500.12708/55777
  • The T-CREST Approach of Compiler and WCET-Analysis Integration / Puschner, P., Prokesch, D., Huber, B., Knoop, J., Hepp, S., & Gebhard, G. (2013). The T-CREST Approach of Compiler and WCET-Analysis Integration. In Proceedings of the 9th Workshop on Software Technologies for Future Embedded and Ubiquitous Systems. 9th Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2013), Paderborn, Deutschland, EU. http://hdl.handle.net/20.500.12708/55037
  • Time-Predictable Code Execution - Instruction-Set Support for the Single-Path Approach / Geyer, C., Huber, B., Prokesch, D., & Puschner, P. (2013). Time-Predictable Code Execution - Instruction-Set Support for the Single-Path Approach. In Proc. 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2013). 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC 2013), Paderborn, Deutschland, Non-EU. http://hdl.handle.net/20.500.12708/55034

2012

  • Compiling for Time Predictability / Puschner, P., Kirner, R., Prokesch, D., & Huber, B. (2012). Compiling for Time Predictability. In Computer Safety, Reliability, and Security SAFECOMP 2012 Workshops: Sassur, ASCoMS, DESEC4LCCI, ERCIM/EWICS, IWDE, Magdeburg, Germany, September 25-28, 2012, Proceedings. ERCIM/EWICS/Cyberphysical Systems Workshop, Magdeburg, Germany, EU. Lecture Notes in Computer Science / Springer. https://doi.org/10.1007/978-3-642-33675-1_35
  • A Formal Framework for Precise Parametric WCET Formulas / Huber, B., Prokesch, D., & Puschner, P. (2012). A Formal Framework for Precise Parametric WCET Formulas. In T. Vardanega (Ed.), 12th International Workshop on Worst-Case Execution Time Analysis, WCET 2012 (pp. 91–102). Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik. https://doi.org/10.4230/OASIcs.WCET.2012.91

2011

  • Using a Local Prefetch Strategy to Obtain Temporal Time Predictability / Cilku, B., & Puschner, P. (2011). Using a Local Prefetch Strategy to Obtain Temporal Time Predictability. In Proc. 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW) (pp. 227–234). IEEE. http://hdl.handle.net/20.500.12708/53923
  • Towards an open timing analysis platform / Huber, B., Puffitsch, W., & Puschner, P. (2011). Towards an open timing analysis platform. In Proceedings of the 11th International Workshop on Worst-Case Execution Time (WCET) Analysis (pp. 6–15). http://hdl.handle.net/20.500.12708/53912

2010

  • Transforming Flow Information during Code Optimization for Timing Analysis / Kirner, R., Puschner, P., & Prantl, A. (2010). Transforming Flow Information during Code Optimization for Timing Analysis. Real-Time Systems, 45(1–2), 72–105. https://doi.org/10.1007/s11241-010-9091-8
  • Time-Predictable Computing / Kirner, R., & Puschner, P. (2010). Time-Predictable Computing. In Time-Predictable Computing (pp. 23–34). http://hdl.handle.net/20.500.12708/53410
  • Avoiding Timing Anomalies Using Code Transformations / Kadlec, A., Kirner, R., & Puschner, P. (2010). Avoiding Timing Anomalies Using Code Transformations. In Avoiding Timing Anomalies Using Code Transformations (pp. 123–132). IEEE. http://hdl.handle.net/20.500.12708/53409
  • Towards a Time-Predictable Hierarchical Memory Architecture - Prefetching Options to be Explored / Cilku, B., & Puschner, P. (2010). Towards a Time-Predictable Hierarchical Memory Architecture - Prefetching Options to be Explored. In 2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops. Proc. 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW 2010), Carmona, Sevilla, Spain, EU. https://doi.org/10.1109/isorcw.2010.22
  • A Code Policy Guaranteeing Fully Automated Path Analysis / Huber, B., & Puschner, P. (2010). A Code Policy Guaranteeing Fully Automated Path Analysis. In A Code Policy Guaranteeing Fully Automated Path Analysis (pp. 80–90). Austrian Computer Society. http://hdl.handle.net/20.500.12708/53183

2009

  • A Single-Path Chip-Multiprocessor System / Schoeberl, M., Puschner, P., & Kirner, R. (2009). A Single-Path Chip-Multiprocessor System. In Software Technologies for Embedded and Ubiquitous Systems (pp. 47–57). Lecture Notes in Computer Science / Springer Verlag. https://doi.org/10.1007/978-3-642-10265-3_5
  • Is Chip-Multiprocessing the End of Real-Time Scheduling? / Schoeberl, M., & Puschner, P. (2009). Is Chip-Multiprocessing the End of Real-Time Scheduling? In Worst-Case Execution Time (WCET) Analsysis (pp. 96–106). Austrian Computer Society. http://hdl.handle.net/20.500.12708/52858
  • Precise Worst-Case Execution Time Analysis for Processors with Timing Anomalies / Kirner, R., Kadlec, A., & Puschner, P. (2009). Precise Worst-Case Execution Time Analysis for Processors with Timing Anomalies. In 2009 21st Euromicro Conference on Real-Time Systems. Euromicro Conference on Real-Time Systems (ECRTS), Delft, Netherlands, Austria. IEEE computer society, CPS. https://doi.org/10.1109/ecrts.2009.8
  • Model-Driven Design and Organic Computing -- Combinable Strategies? / Puschner, P., & Kirner, R. (2009). Model-Driven Design and Organic Computing -- Combinable Strategies? In 2009 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing. IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Newport Beach, CA, USA, Austria. IEEE. https://doi.org/10.1109/isorc.2009.22
  • Towards Composable Timing for Real-Time Software / Puschner, P., Kirner, R., & Pettit, R. G. (2009). Towards Composable Timing for Real-Time Software. In 2009 Software Technologies for Future Dependable Distributed Systems (pp. 1–5). IEEE. http://hdl.handle.net/20.500.12708/52849

2008

  • Measurement-Based Timing Analysis / Wenzel, I., Kirner, R., Rieder, B., & Puschner, P. (2008). Measurement-Based Timing Analysis. In Leveraging Applications of Formal Methods, Verification and Validation (pp. 430–444). Springer Berlin Heidelberg. https://doi.org/10.1007/978-3-540-88479-8_30
  • Hybrid Timing Analysis for ANSI-C Applications with Loops and Function Calls / Rieder, B., & Puschner, P. (2008). Hybrid Timing Analysis for ANSI-C Applications with Loops and Function Calls. In Proceedings of the Junior Scientist Conference 2008 (pp. 101–102). http://hdl.handle.net/20.500.12708/52646
  • Using Model Checking to Derive Loop Bounds of General Loops within ANSI-C Applications for Measurement Based WCET Analysis / Rieder, B., Puschner, P., & Wenzel, I. (2008). Using Model Checking to Derive Loop Bounds of General Loops within ANSI-C Applications for Measurement Based WCET Analysis. In Proceedings of the Sixth Workshop on Intelligent Solutions in Embedded Systems (pp. 3–9). IEEE Computer Society. http://hdl.handle.net/20.500.12708/52593
  • Towards a Common WCET Annotation Language: Essential Ingredients / Kadlec, A., Kirner, R., Puschner, P., Prantl, A., Schordan, M., & Knoop, J. (2008). Towards a Common WCET Annotation Language: Essential Ingredients. In Programmiersprachen und Rechenkonzepte (p. 12). Technischer Bericht des Instituts für Informatik der Christian-Albrechts Universität zu Kiel. http://hdl.handle.net/20.500.12708/52531
  • An Operating System for a Time-Predictable Computing Node / Khyo, G., Puschner, P., & Delvai, M. (2008). An Operating System for a Time-Predictable Computing Node. In Software Technologies for Embedded and Ubiquitous Systems (pp. 150–161). Lecture Notes in Computer Science / Springer Verlag. https://doi.org/10.1007/978-3-540-87785-1_14
  • On Composable System Timing, Task Timing, and WCET Analysis / Puschner, P., & Schoeberl, M. (2008). On Composable System Timing, Task Timing, and WCET Analysis. In Worst-Case Execution Time Analysis; Proceedings of the 8th International Workshop (WCET 2008) (pp. 91–101). Österreichische Computer Gesellschaft. http://hdl.handle.net/20.500.12708/52441
  • Obstacles in Worst-Case Execution Time Analysis / Kirner, R., & Puschner, P. (2008). Obstacles in Worst-Case Execution Time Analysis. In 2008 11th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC). The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, Orlando, Florida, USA, Non-EU. IEEE Computer Society. https://doi.org/10.1109/isorc.2008.65
  • Towards a Common WCET Annotation Languge: Essential Ingredients / Kirner, R., Kadlec, A., Puschner, P., Prantl, A., Schordan, M., & Knoop, J. (2008). Towards a Common WCET Annotation Languge: Essential Ingredients. In Worst-Case Execution Time Analysis; Proceedings of the 8th International Workshop (WCET 2008) (pp. 53–65). Österreichische Computer Gesellschaft. http://hdl.handle.net/20.500.12708/52349

2007

2006

  • Comparing WCET and Resource Demands of Trigonometric Functions Implemented as Iterative Calculations vs. Table-Lookup / Kirner, R., Grössing, M., & Puschner, P. (2006). Comparing WCET and Resource Demands of Trigonometric Functions Implemented as Iterative Calculations vs. Table-Lookup. In 6th Euromicro International Workshop on Worst-Case Execution-Time Analysis (WCET), Proceedings of the (pp. 11–16). http://hdl.handle.net/20.500.12708/51437
  • Portable Data Exchange for Remote-Testing Frameworks / Kirner, R., Puschner, P., Wenzel, I., & Rieder, B. (2006). Portable Data Exchange for Remote-Testing Frameworks. In Proceedings of the Ninth IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing. IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Newport Beach, CA, USA, Austria. IEEE. http://hdl.handle.net/20.500.12708/51434
  • Architecture Support for Temporal Predictability and Composability in Real-Time Computing / Puschner, P. (2006). Architecture Support for Temporal Predictability and Composability in Real-Time Computing. In 4th International Conference on Information and 4th Irish Conference on the Mathematical Foundations of Computer Science and Information Technology, Proceedings. 4th International Conference on Information and 4th Irish Conference on the Mathematical Foundations of Computer Science and Information Technology, Cork, Ireland, EU. http://hdl.handle.net/20.500.12708/51484
  • From Time-Triggered to Time-Deterministic Real-Time Systems / Puschner, P., & Kirner, R. (2006). From Time-Triggered to Time-Deterministic Real-Time Systems. In 5th IFIP Working Conference on Distributed and Parallel Embedded Systems, Proceedings (pp. 115–124). Springer. http://hdl.handle.net/20.500.12708/51435
  • Development of a Framework for Automated Systematic Testing of Safety-Critical Embedded Systems / Kandl, S., Kirner, R., & Puschner, P. (2006). Development of a Framework for Automated Systematic Testing of Safety-Critical Embedded Systems. In 4th Workshop on Intelligent Solutions in Embedded Systems (WISES’06), Proceedings of the. 4th Workshop on Intelligent Solutions in Embedded Systems - (WISES06), Vienna, Austria, Austria. http://hdl.handle.net/20.500.12708/51433

2005

  • Timing Analysis for Embedded Systems and Time-Predictable Computing / Puschner, P., & Kirner, R. (2005). Timing Analysis for Embedded Systems and Time-Predictable Computing. Siemens PSE Technology Day, Vienna, Austria, Austria. http://hdl.handle.net/20.500.12708/84449
  • DECOS-TADE Collaboration / Kim, K., Recker, W., Tsai, W. T., Kopetz, H., & Puschner, P. (2005). DECOS-TADE Collaboration. In IST-NSF Workshop on Transatlantic Research Agenda on Future Challenges in Embedded Systems Design (p. 7). Information Society Technologies/National Science Foundation. http://hdl.handle.net/20.500.12708/51114
  • Experiments with WCET-Oriented Programming and the Single-Path Architecture RR Number / Puschner, P. (2005). Experiments with WCET-Oriented Programming and the Single-Path Architecture RR Number. In Proceedings of the 10th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems, 2005 (pp. 205–210). http://hdl.handle.net/20.500.12708/51095
  • Principles of Timing Anomalies in Superscalar Processors / Wenzel, I., Kirner, R., Puschner, P., & Rieder, B. (2005). Principles of Timing Anomalies in Superscalar Processors. In Proceedings of the Fifth International Conference on Quality Software (pp. 295–303). http://hdl.handle.net/20.500.12708/51092
  • Classification of WCET Analysis Techniques / Kirner, R., & Puschner, P. (2005). Classification of WCET Analysis Techniques. In Proceedings of the 8th IEEE International Symposium on Object-Oriented Real-time distributed Computing (ISORC’05) (pp. 190–199). IEEE Computer Society. http://hdl.handle.net/20.500.12708/51015
  • Measurement-Based Worst-Case Execution Time Analysis / Wenzel, I., Kirner, R., Rieder, B., & Puschner, P. (2005). Measurement-Based Worst-Case Execution Time Analysis. In Proceedings of the third Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS) (pp. 7–10). IEEE. http://hdl.handle.net/20.500.12708/50995
  • Automatic Timing Model Generation by CFG Partitioning and Model Checking / Wenzel, I., Rieder, B., Kirner, R., & Puschner, P. (2005). Automatic Timing Model Generation by CFG Partitioning and Model Checking. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2005) (pp. 606–611). http://hdl.handle.net/20.500.12708/50989
  • Antrag UNI-Infrastruktur III, Embedded Systems Research Cluster / Schmid, U., Kopetz, H., Puschner, P., Mayerhofer, L., Steininger, A., Grünbacher, H., Kastner, W., & Krall, A. (2005). Antrag UNI-Infrastruktur III, Embedded Systems Research Cluster. http://hdl.handle.net/20.500.12708/33035

2004

2003

2002

2001

  • Using Real Hardware to Create an Accurate Timing Model for Execution-Time Analysis / Atanassov, P., Puschner, P., & Kirner, R. (2001). Using Real Hardware to Create an Accurate Timing Model for Execution-Time Analysis. In Proceedings of the IEEE International Workshop on Real-Time Embeeded Systems (in conjunction with 22nd IEEE RTSS 2001). IEEE Workshop on Real-Time Embedded Systems, London, United Kingdom, Austria. http://hdl.handle.net/20.500.12708/50873
  • Impact of DRAM Refresh on the Execution Time of Real-Time Tasks / Atanassov, P., & Puschner, P. (2001). Impact of DRAM Refresh on the Execution Time of Real-Time Tasks. In Proceedings of the International Workshop on Application of Reliable Computing and Communication (in conjunction with PRDC 2001) (pp. 29–34). http://hdl.handle.net/20.500.12708/50874
  • Assumption Coverage under Different Failure Modes in the Time-Triggered Architecture / Bauer, G., Kopetz, H., & Puschner, P. (2001). Assumption Coverage under Different Failure Modes in the Time-Triggered Architecture. In Proceedings of the 8th IEEE International Conference on Emerging Technologies and Factory Automation (pp. 333–341). http://hdl.handle.net/20.500.12708/50882
  • A Profile for High-Integrity Real-Time Java Programs / Puschner, P., & Wellings, A. (2001). A Profile for High-Integrity Real-Time Java Programs. In Proceedings of the 4th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC) (pp. 15–22). http://hdl.handle.net/20.500.12708/50881
  • WCET Analysis of Reusable Portable Code / Puschner, P., & Bernat, G. (2001). WCET Analysis of Reusable Portable Code. In Proceedings of the Euromicro Conference on Real-Time Systems (ECRTS) (pp. 45–52). http://hdl.handle.net/20.500.12708/50879
  • Transformation of Path Information for WCET Analysis during Compilation / Kirner, R., & Puschner, P. (2001). Transformation of Path Information for WCET Analysis during Compilation. In Proceedings of the 13th Euromicro Conference on Real-Time Systems (ECRTS2001) (pp. 29–36). http://hdl.handle.net/20.500.12708/50878
  • WCET Analysis for Systems Modelled in Matlab/Simulink / Kirner, R., Lang, R., & Puschner, P. (2001). WCET Analysis for Systems Modelled in Matlab/Simulink. In Proceedings of the IEEE Real-Time Systems Symposium - Work in Progress Proceedings (pp. 33–36). http://hdl.handle.net/20.500.12708/50872
  • Translating Offline Schedules into Task Attributes for Fixed Priority Scheduling / Dobrin, R., Fohler, G., & Puschner, P. (2001). Translating Offline Schedules into Task Attributes for Fixed Priority Scheduling. In Proceedings of the 22nd IEEE Real-Time Systems Symposium (pp. 225–234). http://hdl.handle.net/20.500.12708/50871

2000

  • A Review of Worst-Case Execution-Time Analysis / Puschner, P., & Burns, A. (2000). A Review of Worst-Case Execution-Time Analysis. Real-Time Systems, 18(2/3), 115–128. http://hdl.handle.net/20.500.12708/174793
  • Supporting Control-Flow-Dependent Execution Times on WCET Calculation / Kirner, R., & Puschner, P. (2000). Supporting Control-Flow-Dependent Execution Times on WCET Calculation. In Proceedings of the WCET2000 (Deutschsprachige WCET-Tagung). Deutschsprachige WCET-Tagung, Paderborn, Germany, Austria. http://hdl.handle.net/20.500.12708/50892
  • Consideration of Optimizing Compilers in the Context of WCET Analysis / Kirner, R., & Puschner, P. (2000). Consideration of Optimizing Compilers in the Context of WCET Analysis. In Proceedings of the Informatiktage 2000, Gesellschaft für Informatik e.V. (pp. 123–126). http://hdl.handle.net/20.500.12708/50891
  • Systems Engineering of Time-Triggered Architectures - The SETTA Approach / Scheidler, C., Puschner, P., Boutin, S., Fuchs, E., Grünsteidl, G., Papadopoulos, Y., Rennhack, J., & Virnich, U. (2000). Systems Engineering of Time-Triggered Architectures - The SETTA Approach. In Proceedings of the 16th IFAC Workshop on Distributed Computer Control Systems (pp. 55–60). http://hdl.handle.net/20.500.12708/50889
  • Integrating WCET Analysis into a Matlab/Simulink Simulation Model / Kirner, R., Lang, R., Puschner, P., & Temple, C. (2000). Integrating WCET Analysis into a Matlab/Simulink Simulation Model. In Proceedings of the 16th IFAC Workshop on Distributed Computer Control Systems (pp. 79–84). http://hdl.handle.net/20.500.12708/50888
  • Low-Level Analysis of a Portable Java Byte Code WCET Analysis Framework / Bate, I., Bernat, G., Murphy, G., & Puschner, P. (2000). Low-Level Analysis of a Portable Java Byte Code WCET Analysis Framework. In Proceedings of the 7th International conference on Real-Time Computing Systems and Applications (pp. 39–48). http://hdl.handle.net/20.500.12708/50887

1993

  • Zeitanalyse von Echtzeitprogrammen / Puschner, P. (1993). Zeitanalyse von Echtzeitprogrammen [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-13642
    Download: PDF (1010 KB)

 

2024

2022

2018

  • Time-predictable memory hierarchy / Chilku, B. (2018). Time-predictable memory hierarchy [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2018.60091
    Download: PDF (1.02 MB)

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

  • Performance Demonstrator / Müller, L. (2002). Performance Demonstrator [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/185221

2001

 

  • Gründungsmitglied der IFIP 10.2 WG on Embedded Systems
    2006 / IFIP
  • Marie-Curie Fellowship
    1999 / EC Europäische Komission - Marie Curie

Soon, this page will include additional information such as reference projects, activities as journal reviewer and editor, memberships in councils and committees, and other research activities.

Until then, please visit Peter Puschner’s research profile in TISS .