2024W

• Bachelor Thesis for Computer Science and Business Informatics / 182.715 / PR

2025S

• Bachelor Thesis for Computer Science and Business Informatics / 182.715 / PR
• Dependable Systems / 191.109 / VU

• Time-Triggered Architecture: A Consistent Computing Platform / Maier, R., Bauer, G., Stöger, G., & Poledna, S. (2002). Time-Triggered Architecture: A Consistent Computing Platform. http://hdl.handle.net/20.500.12708/32851
• Tolerating Arbitrary Node Failures in the Time-Triggered Architecture / Kopetz, H., Bauer, G., & Poledna, S. (2001). Tolerating Arbitrary Node Failures in the Time-Triggered Architecture. In Proceedings of the SAE 2001 World Congress. SAE World Congress, Detroit, MI, USA, Austria. http://hdl.handle.net/20.500.12708/50884
• Replica Determinism and Flexible Scheduling in Hard Real-Time Dependable Systems / Poledna, S., Barrett, P., Burns, A., & Wellings, A. (2000). Replica Determinism and Flexible Scheduling in Hard Real-Time Dependable Systems. IEEE Transactions on Computers, 49(2), 100–111. http://hdl.handle.net/20.500.12708/174794

• Increased efficiency through test automation in electronics development / Kratochwill, M. (2019). Increased efficiency through test automation in electronics development [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/78715
• Software fault-injection in a TTEthernet Cluster / Bija, R.-F. (2018). Software fault-injection in a TTEthernet Cluster [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/158475
• Automated synthesis of behavior-driven integration tests for embedded systems / Niederstätter, E. (2017). Automated synthesis of behavior-driven integration tests for embedded systems [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2017.34202
  Download: PDF (2.07 MB)
• Time-triggered communication in hybrid network toplologies / Zischka, W. (2015). Time-triggered communication in hybrid network toplologies [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2015.28996
• Clock synchronization gateway between SAE AS6802 and IEEE 1588 / Mödlhamer, S. (2014). Clock synchronization gateway between SAE AS6802 and IEEE 1588 [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/79461
• SAE AS6802 SW-based end system for AUTOSAR / Frühwirth, T. (2014). SAE AS6802 SW-based end system for AUTOSAR [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/78854
• Evaluation and implementation of a mixed TTEthernet and AVB Network / Rebernig, S. (2012). Evaluation and implementation of a mixed TTEthernet and AVB Network [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/160593
• A distributed platform for integrated modular avionics / Wolfig, R. (2008). A distributed platform for integrated modular avionics [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-25160
  Download: PDF (1.53 MB)
• Fault-tolerant network alignment in TTP/C / Wohlmuth, J. (2008). Fault-tolerant network alignment in TTP/C [Master Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/182079
• The poisonnode : development and evaluation of a TTP/C disturbance device / Walkner, G. (2003). The poisonnode : development and evaluation of a TTP/C disturbance device [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/185826
• Event communication on TTP/C / Rumpler, B. (2002). Event communication on TTP/C [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/181295
• TTP/C-Restbussimulation mit Simulink / Schlager, M. (2002). TTP/C-Restbussimulation mit Simulink [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/181252