2024W

• Bachelor Thesis for Informatics and Business Informatics / 185.A16 / PR
• Code Generators / 185.416 / VO
• Compilerdesign seminar / 185.A22 / SE
• Computer Engineering Project / 185.A96 / PR
• Orientation Informatics and Business Informatics / 180.766 / VU
• Programming Paradigms / 194.023 / VU
• Project in Computer Science 1 / 194.145 / PR
• Project in Computer Science 2 / 194.146 / PR
• Project in Medical Informatics / 185.A30 / PR
• Scientific Project Computer Engineering / 185.A97 / PR
• Scientific Research and Writing / 193.052 / SE
• Seminar for Master Students in Software Engineering & Internet Computing / 180.777 / SE
• Seminar for PhD Students / 185.A24 / SE

2025S

• Project in Computer Science 1 / 194.145 / PR
• Project in Computer Science 2 / 194.146 / PR

• Correct compilers for correct application specific processors
  2010 – 2015 / Austrian Research Promotion Agency (FFG)
  Publications: 54411 / 54412 / 54544 / 54693
• Optimal Code Generation for Explicitly Parallel Processors
  2009 – 2013 / Austrian Science Fund (FWF)
  Publications: 53123 / 53124 / 53172 / 53173 / 53307 / 53477 / 53627 / 53968 / 53969 / 53970 / 54713 / 54833 / 84989 / 85543 / 85644
• CD Labor - Compilation Techniques for Embedded Processors Modul Clustered Processors
  2005 – 2009 / Christian Doppler Research Association (CDG)
• CD Labor - Compilation Techniques for Embedded Processors
  2002 – 2009 / Christian Doppler Research Association (CDG)
• Cacao
  1996 – 2025 / Cacao Virtual Machine

2024

• The Vienna Architecture Description Language / Himmelbauer, S., Hochrainer, C., Huber, B. L., Mischkulnig, N., Paulweber, P., Schwarzinger, T., & Krall, A. (2024). The Vienna Architecture Description Language. arXiv. https://doi.org/10.34726/5619
  Download: PDF (1.01 MB)

2023

• A pred-LL(*) parsable typed higher-order macro system for architecture description languages / Hochrainer, C., & Krall, A. (2023). A pred-LL(*) parsable typed higher-order macro system for architecture description languages. In C. De Roover, B. Rumpe, & A. Shaikhha (Eds.), Proceedings of the 22nd ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences (pp. 29–41). https://doi.org/10.1145/3624007.3624052
  Download: PDF (228 KB)

2022

• Instruction Code Selection / Ebner, D., Krall, A., & Scholz, B. (2022). Instruction Code Selection. In F. Rastello & F. Bouchez Tichadou (Eds.), SSA-based Compiler Design (pp. 257–268). Springer. https://doi.org/10.1007/978-3-030-80515-9_19

2018

• Fast and flexible instruction selection with constraints / Thier, P., Ertl, M. A., & Krall, A. (2018). Fast and flexible instruction selection with constraints. In Proceedings of the 27th International Conference on Compiler Construction. Compiler Construction, Wien, Austria. ACM. https://doi.org/10.1145/3178372.3179501

2016

• Vectorization in PyPy's Tracing Just-In-Time Compiler / Plangger, R., & Krall, A. (2016). Vectorization in PyPy’s Tracing Just-In-Time Compiler. In Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems. SCOPES 2016 - 19th International Workshop on Software and Compilers for Embedded Systems, St. Goar, EU. https://doi.org/10.1145/2906363.2906384

2015

• PyPy's Number Crunching Optimization / Plangger, R., & Krall, A. (2015). PyPy’s Number Crunching Optimization. In Programmiersprachen und Grundlagen der Programmierung (pp. 448–462). Schriftenreihe des Instituts für Computersprachen, TU Wien. http://hdl.handle.net/20.500.12708/56436
• vanHelsing: A Fast Proof Checker for Debuggable Compiler Verification / Lezuo, R., Dragan, I., Barany, G., & Krall, A. (2015). vanHelsing: A Fast Proof Checker for Debuggable Compiler Verification. In L. Kovacs & D. Zaharie (Eds.), 2015 17th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC). https://doi.org/10.1109/synasc.2015.34

2014

• CASM / Lezuo, R., Paulweber, P., & Krall, A. (2014). CASM. In Proceedings of the 2014 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems - LCTES ’14. LCTES ’14: 2014 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems, Edinburgh, UK, EU. https://doi.org/10.1145/2597809.2597813
• Correct Compilers for Correct Processors / Krall, A. (2014). Correct Compilers for Correct Processors. HiPEAC 2014 (International Conference on High-Performance and Embedded Architectures and Compilers), Vienna, Austria. http://hdl.handle.net/20.500.12708/86025
• Integrated modulo scheduling and cluster assignment for TI TMS320C64x+ architecture / Kim, N., & Krall, A. (2014). Integrated modulo scheduling and cluster assignment for TI TMS320C64x+ architecture. In Proceedings of the 11th Workshop on Optimizations for DSP and Embedded Systems - ODES ’14. ODES-11: 11th Workshop on Optimizations for DSP and Embedded Systems, Orlando, USA, Non-EU. https://doi.org/10.1145/2568326.2568327

2013

• Optimal and Heuristic Global Code Motion for Minimal Spilling / Barany, G., & Krall, A. (2013). Optimal and Heuristic Global Code Motion for Minimal Spilling. In Compiler Construction 22nd International Conference, CC 2013, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2013, Rome, Italy, March 16-24, 2013, Proceedings (pp. 21–40). Lecture Notes in Computer Science. https://doi.org/10.1007/978-3-642-37051-9_2
• Software De-Pipelining for Nested Loops / Bermudo, N., Krall, A., Su, B., & Wang, J. (2013). Software De-Pipelining for Nested Loops. International Journal of Computer Science and Electronics Engineering, 1(1), 6. http://hdl.handle.net/20.500.12708/157927
• IR-level versus machine-level if-conversion for predicated architectures / Jordan, A., Kim, N., & Krall, A. (2013). IR-level versus machine-level if-conversion for predicated architectures. In Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems - ODES ’13. 10th Workshop on Optimizations for DSP and Embedded Systems, Shenzen, China, Non-EU. ACM. https://doi.org/10.1145/2443608.2443611
  Project: EPICOpt (2009–2013)
• CASM: Implementing an Abstract State Machine based programming language / Lezuo, R., Barany, G., & Krall, A. (2013). CASM: Implementing an Abstract State Machine based programming language. In Software Engineering 2013, Workshopband, (inkl. Doktorandensymposium) (pp. 75–90). GI-Edition - Lecture Notes in Informatics (LNI). http://hdl.handle.net/20.500.12708/54693
  Project: C3Pro (2010–2015)
• Using the CASM language for simulator synthesis and model verification / Lezuo, R., & Krall, A. (2013). Using the CASM language for simulator synthesis and model verification. In Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation Methods and Tools - RAPIDO ’13. RAPIDO’13, Berlin, EU. https://doi.org/10.1145/2432516.2432522
  Project: C3Pro (2010–2015)

2012

• Using Semantic Relatedness and Locality for Requirements Elicitation Guidance / Farfeleder, S., Moser, T., & Krall, A. (2012). Using Semantic Relatedness and Locality for Requirements Elicitation Guidance. In Proceedings of the 24th International Conference on Software Engineering and Knowledge Engineering (SEKE’2012), Hotel Sofitel, Redwood City, San Francisco Bay, USA July 1-3, 2012 (pp. 19–24). http://hdl.handle.net/20.500.12708/54550
• Special Issue: Compilers for Parallel Computing (CPC 2010) (Editorial) / Krall, A., & Barany, G. (2012). Special Issue: Compilers for Parallel Computing (CPC 2010) (Editorial). Concurrency and Computation: Practice and Experience, 24(5), 443–444. http://hdl.handle.net/20.500.12708/163461
• A Unified Processor Model for Compiler Verification and Simulation Using ASM / Lezuo, R., & Krall, A. (2012). A Unified Processor Model for Compiler Verification and Simulation Using ASM. In Abstract State Machines, Alloy, B, VDM, and Z (pp. 327–330). https://doi.org/10.1007/978-3-642-30885-7_24
  Project: C3Pro (2010–2015)

2011

• Computation of Alias Sets from Shape Graphs for Comparison of Shape Analysis Precision / Pavlu, V., Schordan, M., & Krall, A. (2011). Computation of Alias Sets from Shape Graphs for Comparison of Shape Analysis Precision. In Proceedings of the Eleventh IEEE International Workshop on Source Code Analysis and Manipulation (pp. 25–34). IEEE. http://hdl.handle.net/20.500.12708/53969
  Project: EPICOpt (2009–2013)
• Parametrizing Motion Controllers of Humanoid Robots by Evolution / Schreiner, D., Punzengruber, C., & Krall, A. (2011). Parametrizing Motion Controllers of Humanoid Robots by Evolution. INFORMATIK 2011, Berlin, Germany. http://hdl.handle.net/20.500.12708/85318
• Ontology-Driven Guidance for Requirements Elicitation / Farfeleder, S., Moser, T., Krall, A., Stalhane, T., Omoronyia, I., & Zojer, H. (2011). Ontology-Driven Guidance for Requirements Elicitation. In Proceedings of 8th Extended Semantic Web Conference (ESWC 2011) (pp. 1–15). http://hdl.handle.net/20.500.12708/53801
• DODT: Increasing Requirements Formalism using Domain Ontologies for Improved Embedded Systems Development / Farfeleder, S., Moser, T., Krall, A., Stalhane, T., Zojer, H., & Panis, C. (2011). DODT: Increasing Requirements Formalism using Domain Ontologies for Improved Embedded Systems Development. In Proceedings of 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011) (pp. 1–4). http://hdl.handle.net/20.500.12708/53800
• Modeling Application-Specific Processors for the Use in Cyber-Physical Systems / Brandner, F., Pavlu, V., & Krall, A. (2011). Modeling Application-Specific Processors for the Use in Cyber-Physical Systems. In Informatik 2011. 41. Jahrestagung der Gesellschaft für Informatik, Berlin, Deutschland, EU. Gesellschaft für Informatik e.V. (GI). http://hdl.handle.net/20.500.12708/53970
  Project: EPICOpt (2009–2013)
• Optimal Code Generation for Explicitly Parallel Processors / Krall, A. (2011). Optimal Code Generation for Explicitly Parallel Processors. ETH Informatics Seminar, Zuerich, Non-EU. http://hdl.handle.net/20.500.12708/85317
• Efficient Instruction Set Simulation with Abstract State Machines / Krall, A. (2011). Efficient Instruction Set Simulation with Abstract State Machines. DIKU Seminar, Kopenhagen, Denmark, EU. http://hdl.handle.net/20.500.12708/85279
• Optimal Code Generation for Explicitly Parallel Processors / Krall, A. (2011). Optimal Code Generation for Explicitly Parallel Processors. Informatics Seminar, Lugano, Schweiz, Non-EU. http://hdl.handle.net/20.500.12708/85278
• Efficient Instruction Set Simulation with Abstract State Machines / Krall, A. (2011). Efficient Instruction Set Simulation with Abstract State Machines. Seminar, Ecole Centrale Paris, EU. http://hdl.handle.net/20.500.12708/85277
• Optimal Code Generation for Explicitly Parallel Processors / Krall, A. (2011). Optimal Code Generation for Explicitly Parallel Processors. SasSeminar, Linkoping Schweden, EU. http://hdl.handle.net/20.500.12708/85276

2010

• Execution models for processors and instructions / Brandner, F., Pavlu, V., & Krall, A. (2010). Execution models for processors and instructions. In NORCHIP 2010. Norchip 2010, Tampere, Finland, EU. IEEE Proceedings. https://doi.org/10.1109/norchip.2010.5669478
  Project: EPICOpt (2009–2013)
• Optimistic Integrated Instruction Scheduling and Register Allocation / Barany, G., & Krall, A. (2010). Optimistic Integrated Instruction Scheduling and Register Allocation. In 15th Workshop on Compilers for Parallel Computing (CPC 2010) (p. 15). http://hdl.handle.net/20.500.12708/53172
  Project: EPICOpt (2009–2013)
• Optimistic Integrated Instruction Scheduling and Register Allocation / Barany, G., & Krall, A. (2010). Optimistic Integrated Instruction Scheduling and Register Allocation. ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES 2010), Stockholm, Schweden, EU. http://hdl.handle.net/20.500.12708/84989
  Project: EPICOpt (2009–2013)
• Effective Tool Generation by Architecture Description / Krall, A. (2010). Effective Tool Generation by Architecture Description. ICSA Colloquium Talk, University of Edinburgh, EU. http://hdl.handle.net/20.500.12708/85080
• Fast JIT Code Generation for x86-64 with LLVM / Pavlu, V., & Krall, A. (2010). Fast JIT Code Generation for x86-64 with LLVM. In ACACES 2011 Poster Abstracts (pp. 289–290). HiPEAC. http://hdl.handle.net/20.500.12708/53968
  Project: EPICOpt (2009–2013)
• Evaluating Java runtime reflection for implementing cross-language method invocations / Sobernig, S., & Zdun, U. (2010). Evaluating Java runtime reflection for implementing cross-language method invocations. In A. Krall & H.-P. Mössenböck (Eds.), Proceedings of the 8th International Conference on the Principles and Practice of Programming in Java - PPPJ ’10. ACM. https://doi.org/10.1145/1852761.1852781
• Optimal and Heuristic Code Generation for Explicitly Parallel Processors / Barany, G., Jordan, A., Pavlu, V., & Krall, A. (2010). Optimal and Heuristic Code Generation for Explicitly Parallel Processors. In ACACES 2010 Poster Abstracts (pp. 87–88). HiPEAC. http://hdl.handle.net/20.500.12708/53173
  Project: EPICOpt (2009–2013)
• Optimistic Integrated Instruction Scheduling and Register Allocation / Barany, G., & Krall, A. (2010). Optimistic Integrated Instruction Scheduling and Register Allocation. In Proceedings of the Junior Scientist Conference 2010 (pp. 97–98). http://hdl.handle.net/20.500.12708/53123
  Project: EPICOpt (2009–2013)
• PPPJ'10 Proceedings of the 8th International Conference on the Principles and Practice of Programming in Java / Krall, A., & Mössenböck, H.-P. (Eds.). (2010). PPPJ’10 Proceedings of the 8th International Conference on the Principles and Practice of Programming in Java. ACM. http://hdl.handle.net/20.500.12708/23282

2009

• 08441 Final Report -- Emerging Uses and Paradigms for Dynamic Binary Translation / Altman, E., Childers, B. R., Cohn, R., Davidson, J., Brosschere, K. D., Sutter, B. D., Ertl, M. A., Franz, M., Gu, Y., Hauswirth, M., Heinz, T., Hsu, W.-C., Knoop, J., Krall, A., Kumar, N., Maebe, J., Muth, R., Rival, X., Rohou, E., … Vick, C. (2009). 08441 Final Report -- Emerging Uses and Paradigms for Dynamic Binary Translation. In Emerging Uses and Paradigms for Dynamic Binary Translation (No. 08441). Schloss Dagstuhl - Leibniz-Zentrum für Informatik. https://doi.org/10.4230/DagSemProc.08441.2
  Project: ALL-TIMES (2007–2010)
• Progressive spill code placement / Ebner, D., Scholz, B., & Krall, A. (2009). Progressive spill code placement. In Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems - CASES ’09. International Conference on Compilers, Architecture and Synthesis for Embedded Systems [CASES 07], Salzburg, Austria, Austria. https://doi.org/10.1145/1629395.1629408
• Fast and Accurate Simulation Using the LLVM Compiler Framework / Brandner, F., Fellnhofer, A., Krall, A., & Riegler, D. (2009). Fast and Accurate Simulation Using the LLVM Compiler Framework. In S. Niar, R. Leupers, & O. Temam (Eds.), 1st Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (p. 6). http://hdl.handle.net/20.500.12708/53601
• Stack allocation of objects in the CACAO virtual machine / Molnar, P., Krall, A., & Brandner, F. (2009). Stack allocation of objects in the CACAO virtual machine. In B. Stephenson & C. W. Probst (Eds.), Proceedings of the 7th International Conference on Principles and Practice of Programming in Java - PPPJ ’09. https://doi.org/10.1145/1596655.1596680

2008

• Optimizations for Object-Oriented Languages / Krall, A., & Horspool, N. (2008). Optimizations for Object-Oriented Languages. In Y. N. Srikant & P. Shankar (Eds.), The COMPILER DESIGN Handbook: Optimizations and Machine Code Generation (second edition) (pp. 13-1-13–29). CRC Press. http://hdl.handle.net/20.500.12708/26197
• Generalized instruction selection using<i>SSA</i>-graphs / Ebner, D., Brandner, F., Scholz, B., Krall, A., Wiedermann, P., & Kadlec, A. (2008). Generalized instruction selection usingSSA-graphs. In Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems - LCTES ’08. ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, Ottawa, Canada, Non-EU. ACM - Association for Computing Machinery. https://doi.org/10.1145/1375657.1375663
• Dynamic Binary Translation for Generation of Cycle Accurate Architecture Simulators / Fellnhofer, A., Krall, A., & Riegler, D. (2008). Dynamic Binary Translation for Generation of Cycle Accurate Architecture Simulators. Emerging Uses and Paradigms for Dynamic Binary Translation, Schloss Dagstuhl, EU. http://hdl.handle.net/20.500.12708/84821

2007

• Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures / Farfeleder, S., Krall, A., & Horspool, N. (2007). Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures. The Journal of Systems Architecture: Embedded Software Design, 53(8), 501–510. https://doi.org/10.1016/j.sysarc.2006.11.003
• Adaptive inlining and on-stack replacement in the CACAO virtual machine / Steiner, E., Krall, A., & Thalinger, C. (2007). Adaptive inlining and on-stack replacement in the CACAO virtual machine. In L. Veiga (Ed.), Proceedings of the 5th international symposium on Principles and practice of programming in Java  - PPPJ ’07. ACM International Conference Proceeding Series. https://doi.org/10.1145/1294325.1294356
• Instruction Set Encoding Optimization for Code Size Reduction / Med, M., & Krall, A. (2007). Instruction Set Encoding Optimization for Code Size Reduction. In H. Blume, G. Gaydadjiev, J. Glossner, & P. Knijnenburg (Eds.), 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. IEEE. https://doi.org/10.1109/icsamos.2007.4285728
• Leveraging Predicated Execution for Multimedia Processing / Ebner, D., Brandner, F., & Krall, A. (2007). Leveraging Predicated Execution for Multimedia Processing. In S. Samarjit Chakraborty (Ed.), 2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia. IEEE. https://doi.org/10.1109/estmed.2007.4375809
• Compiler generation from structural architecture descriptions / Brandner, F., Ebner, D., & Krall, A. (2007). Compiler generation from structural architecture descriptions. In A. Donlin (Ed.), Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems  - CASES ’07. ACM. https://doi.org/10.1145/1289881.1289886

2006

• Compiler Optimizations for Processors with SIMD Instructions / Pryanishnikov, I., Krall, A., & Horspool, N. (2006). Compiler Optimizations for Processors with SIMD Instructions. Software: Practice and Experience, 37(No 1), 93–113. http://hdl.handle.net/20.500.12708/173437
• Effective Compiler Generation by Architecture Description / Farfeleder, S., Krall, A., & Steiner, E. (2006). Effective Compiler Generation by Architecture Description. In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (pp. 145–152). ACM. http://hdl.handle.net/20.500.12708/51666
• Short Presentation: Static Verification of Global Heap References in Java Native Libraries / Krall, A., Thalinger, C., Ebner, D., & Brandner, F. (2006). Short Presentation: Static Verification of Global Heap References in Java Native Libraries. In Proceedings of the Third workshop on Semantics, Program Analysis, and Computing Environments for memory management (pp. 98–100). http://hdl.handle.net/20.500.12708/51665
• Superinstructions and Replication in the Cacao JVM interpreter / Ertl, M. A., Thalinger, C., & Krall, A. (2006). Superinstructions and Replication in the Cacao JVM interpreter. Journal of .NET Technologies, VOL. 4(ISBN 80-86943-13-5), 25–32. http://hdl.handle.net/20.500.12708/173416
• Effective Tool Generation by Architecture Description / Krall, A. (2006). Effective Tool Generation by Architecture Description. Informatik Kolloquium, TU Muenchen, Garching, Deutschland, Austria. http://hdl.handle.net/20.500.12708/84553
• Effective Tool Generation by Architecture Description / Krall, A. (2006). Effective Tool Generation by Architecture Description. Informatik Kolloquium, TU Muenchen, Garching, Deutschland, Austria. http://hdl.handle.net/20.500.12708/84552
• Effective Tool Generation by Architecture Description / Krall, A. (2006). Effective Tool Generation by Architecture Description. Informatik Kolloquium, TU Muenchen, Garching, Deutschland, Austria. http://hdl.handle.net/20.500.12708/84551
• Effective Compiler Generation by Architecture Description / Krall, A. (2006). Effective Compiler Generation by Architecture Description. Informatik Kolloquium, TU Muenchen, Garching, Deutschland, Austria. http://hdl.handle.net/20.500.12708/84550

2005

• Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures / Farfeleder, S., Krall, A., & Horspool, N. (2005). Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures. In Embedded Computer Systems: Architectures, Modeling, and Simulation (pp. 222–231). Springer Verlag. https://doi.org/10.1007/11512622_24
• Control Flow Graph Reconstruction for Assembly Language Programs with Delayed Instructions / Bermudo, N., Krall, A., & Horspool, N. (2005). Control Flow Graph Reconstruction for Assembly Language Programs with Delayed Instructions. In Proceedings of the Fifth IEEE International Workshop on Source Code Analysis and Manipulation (pp. 107–116). IEEE Press. http://hdl.handle.net/20.500.12708/51242
• Antrag UNI-Infrastruktur III, Embedded Systems Research Cluster / Schmid, U., Kopetz, H., Puschner, P., Mayerhofer, L., Steininger, A., Grünbacher, H., Kastner, W., & Krall, A. (2005). Antrag UNI-Infrastruktur III, Embedded Systems Research Cluster. http://hdl.handle.net/20.500.12708/33035

2004

• A Scalable DSP Core for SoC Applications / Panis, C., Hirnschrott, U., Krall, A., Farfeleder, S., Laure, G., Lazian, W., & Nurmi, J. (2004). A Scalable DSP Core for SoC Applications. In Proceedings of the International Symposium on System-On-Chip (SOC’04) (pp. 85–88). IEEE. http://hdl.handle.net/20.500.12708/50988

2023

• Optimised processor simulation with VADL / Mihaylov, H. (2023). Optimised processor simulation with VADL [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2023.102629
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2022

• Flexible generation of low-level developer tools with VADL / Schwarzinger, T. (2022). Flexible generation of low-level developer tools with VADL [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2023.103246
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• An SSA-based register allocator for the Glasgow Haskell compiler / Maurer, B. (2022). An SSA-based register allocator for the Glasgow Haskell compiler [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2022.90764
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2021

• Compiler backend generation using the VADL processor description language / Graf, A. (2021). Compiler backend generation using the VADL processor description language [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2021.79221
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2020

• Cycle-Accurate simulator generator for the VADL processor description language / Schützenhöfer, H. (2020). Cycle-Accurate simulator generator for the VADL processor description language [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2021.78460
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• Efficient cycle detection on a partially reference counted heap / Beyer, S. (2020). Efficient cycle detection on a partially reference counted heap [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2020.44470
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2019

• Generational and parallel garbage collection / Inführ, D. (2019). Generational and parallel garbage collection [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2019.62350
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2015

• Migrating IBM HLASM to C / Wilhelm, J. (2015). Migrating IBM HLASM to C [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2015.27852
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• PyPy's number crunching optimization : just-in-time superword parallelism / Plangger, R. (2015). PyPy’s number crunching optimization : just-in-time superword parallelism [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2015.29423
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• Instruction selection for the CACAO VM / Kühmayer, C. (2015). Instruction selection for the CACAO VM [Master Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2015.27943
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• Integrated code motion and register allocation / Bárány, G. (2015). Integrated code motion and register allocation [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2015.29461
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2014

• Invokedynamic for the CACAO JVM / Gruber, F. (2014). Invokedynamic for the CACAO JVM [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2014.23038
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• Scalable translation validation : tools, techniques and framework / Lezuo, R. (2014). Scalable translation validation : tools, techniques and framework [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2014.24883
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• An optimizing compiler for the abstract state machine language CASM / Paulweber, P. (2014). An optimizing compiler for the abstract state machine language CASM [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2014.24884
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• On worst-case execution time analysis and optimization / Jordan, A. (2014). On worst-case execution time analysis and optimization [Dissertation, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2014.23732
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2013

• Optimization framework for the CACAO VM / Eisl, J. (2013). Optimization framework for the CACAO VM [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://doi.org/10.34726/hss.2013.23350
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• Implementation of a Java just-in-time compiler in Haskell / Urban, B. (2013). Implementation of a Java just-in-time compiler in Haskell [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-56149
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2012

• Requirements specification and analysis for embedded systems / Farfeleder, S. (2012). Requirements specification and analysis for embedded systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-52549
  Download: PDF (1.51 MB)

2011

• Exact garbage collection for the cacao virtual machine / Starzinger, M. (2011). Exact garbage collection for the cacao virtual machine [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-38559
  Download: PDF (624 KB)

2010

• Efficient profiling in the LLVM compiler infrastructure / Neustifter, A. (2010). Efficient profiling in the LLVM compiler infrastructure [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-36698
  Download: PDF (550 KB)

2009

• SSA-based code generation techniques for embedded architectures / Ebner, D. (2009). SSA-based code generation techniques for embedded architectures [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-36109
  Download: PDF (1.92 MB)
• Compiler backend generation from structural processor models / Brandner, F. (2009). Compiler backend generation from structural processor models [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-32992
  Download: PDF (1.28 MB)
• Escape analysis and stack allocation of Java objects in the CACAO VM / Molnár, P. (2009). Escape analysis and stack allocation of Java objects in the CACAO VM [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-26787
  Download: PDF (643 KB)

2008

• Software Pipelining in a C-Compiler / Huber, B. L. (2008). Software Pipelining in a C-Compiler [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-25657
  Download: PDF (522 KB)
• Type analysis in a Java Virtual Machine / Oates, C. (2008). Type analysis in a Java Virtual Machine [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-25637
  Download: PDF (942 KB)
• Implementation of native threads and locks in the CACAO Java Virtual Machine / Ring, S. (2008). Implementation of native threads and locks in the CACAO Java Virtual Machine [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-27782
  Download: PDF (770 KB)
• Automatic generation of interpreting instruction set simulators / Fellnhofer, A. (2008). Automatic generation of interpreting instruction set simulators [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-25739
  Download: PDF (722 KB)
• Dynamic binary translation for automatically generated simulators / Rigler, D. (2008). Dynamic binary translation for automatically generated simulators [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-28911
  Download: PDF (725 KB)
• Profile guided code positioning optimizations in a C-compiler / Kim, N. (2008). Profile guided code positioning optimizations in a C-compiler [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/179729

2007

• Porting the CACAO virtual machine to POWERPC64 and Coldfire / Lezuo, R. R. (2007). Porting the CACAO virtual machine to POWERPC64 and Coldfire [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-18628
  Download: PDF (1010 KB)
• Adaptive inlining and on-stack replacement in a Java virtual machine / Steiner, E. (2007). Adaptive inlining and on-stack replacement in a Java virtual machine [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-95395
  Download: PDF (564 KB)
• Porting the CACAO virtual machine to SPARC / Jordan, A. (2007). Porting the CACAO virtual machine to SPARC [Master Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/184132
• Static program analyses and code transformations for DSP software / Pryanishnikov, I. (2007). Static program analyses and code transformations for DSP software [Dissertation, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/178671

2006

• Creating a GCC back end for a VLIW-architecture / Prantl, A. (2006). Creating a GCC back end for a VLIW-architecture [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-36548
  Download: PDF (476 KB)
• Instruction set encoding optimization for code size reduction / Med, M. (2006). Instruction set encoding optimization for code size reduction [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/181329

2005

• Reverse compilation techniques for VLIW architectures / Bermudo Pla, N. (2005). Reverse compilation techniques for VLIW architectures [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-19318
  Download: PDF (1.07 MB)
• Compilation techniques for reducing energy consumption of embedded digital signal processors / Hirnschrott, U. (2005). Compilation techniques for reducing energy consumption of embedded digital signal processors [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-20049
  Download: PDF (4.72 MB)
• Compiler generation by architecture description / Farfeleder, S. (2005). Compiler generation by architecture description [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/182696

2004

• Instruction set simulation : für die VSP Architektur / Brandner, F. (2004). Instruction set simulation : für die VSP Architektur [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/177969
• Software pipelining in a DSP C-Compiler / Ogris, J. (2004). Software pipelining in a DSP C-Compiler [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/177964
• Optimizing and porting the CACAO JVM / Thalinger, C. (2004). Optimizing and porting the CACAO JVM [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/177961

2003

• Code optimizations for digital signal processors / Eckstein, E. (2003). Code optimizations for digital signal processors [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-12005
  Download: PDF (6.85 MB)
• An optimizing high-level linker / Wögerer, P. (2003). An optimizing high-level linker [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/183632

2002

• A DSP C-Compiler / Vögler, K. (2002). A DSP C-Compiler [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/186284
• Implementation of Java virtual machines for high-performance multi-processor systems using cache-coherent non-uniform memory architectures / Tomsich, P. R. (2002). Implementation of Java virtual machines for high-performance multi-processor systems using cache-coherent non-uniform memory architectures [Dissertation, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/178878

2001

• DSP compiler optimization / Hirnschrott, U. (2001). DSP compiler optimization [Diploma Thesis, Technische Universität Wien]. reposiTUm. http://hdl.handle.net/20.500.12708/179676

• Heinz Zemanek Preis
  1987 / Austria / Website

Soon, this page will include additional information such as reference projects, activities as journal reviewer and editor, memberships in councils and committees, and other research activities.

Until then, please visit Andreas Krall’s research profile in TISS .