About

Ing-Chao Lin received his PhD from the Department of Computer Science and Engineering at Pennsylvania State University in 2007. From 2007 to 2009, he was a staff R&D engineer at Real Intent Inc., where he worked on Real Intent’s automatic timing exception verifier for design constraints of integrated circuits. He joined the Department of Computer Science and Information Engineering of the National Cheng Kung University in 2009, where he is currently a Full Professor. Additionally, he was a Visiting Scholar at the University of California from 2015 to 2016, at Academia Sinica in Taiwan in 2017, and at the Technical University of Munich from 2022 to 2023. His research interests include computer-aided design for nanoscale silicon, design for reliability, memory-centric architecture, and artificial intelligence on chips. He has authored or co-authored over 60 top-notch journal and conference papers and has served on the technical program committees for prestigious conferences, including DAC, ICCAD, ICCD, and ASP-DAC. He has been an IEEE Senior Member since 2014 and an ACM Senior Member since 2016. He was the recipient of the 2015 Excellent Young Researcher Award, bestowed by the Chinese Institute of Electrical Engineering; the Best Young Professionals (Formerly GOLD) award, awarded by the IEEE Tainan Section in 2016; and the Outstanding Youth of Tainan City, Taiwan, 2020. He received the Humboldt Fellowship for Experienced Researchers from the Alexander von Humboldt Foundation in Germany from 2019 to 2023. He received the Outstanding TPC member award at DAC 2024 and the Best Paper Award at the Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), 2024, and the International Symposium on Quality Electronic Design (ISQED), 2025.

Abstract

Fault-Tolerant Energy-Efficient RRAM-based Computing

In the era of big data and artificial intelligence, the von Neumann bottleneck, a limitation caused by data movement between the CPU and memory, poses significant challenges to system energy efficiency and performance. This has led researchers to explore processing-in-memory (PIM) architectures, which perform operations within the memory to reduce latency and energy consumption associated with data transfer. Meanwhile, processing-in-memory architectures minimize data movement and enhance energy efficiency, which mirrors how the human brain processes information, leading to its classification as neuromorphic computing. Among the PIM architectures, Resistive RAM (RRAM)-based neuromorphic computing stands out for its high density, CMOS compatibility, and low leakage characteristics. However, the RRAM-based architecture faces hurdles such as extended programming times, reliability issues, and variations due to manufacturing limitations. To address these issues, it is crucial to optimize programming efficiency and improve fault tolerance. In this talk, Ing-Chao Lin will introduce the basics of RRAM-based neuromorphic computing and highlight its challenges. He will then present recent research progress in improving programming efficiency and fault tolerance in these architectures. With the proposed approach, the programming efficiency and fault tolerance capability of RRAM-based neuromorphic computing architectures are significantly improved.

About Current Trends in Computer Science

This lecture is part of the Current Trends in Computer Science Lecture Series by the TU Wien Informatics Doctoral School, where renowned Guest Professors hold public lectures every semester. If you are studying with us, the lecture series can be credited as an elective course for students of master programs of computer science: 195.072 Current Trends in Computer Science. Additionally, you can join courses held by this year’s Guest Professors of our doctoral colleges and the TU Wien Informatics Doctoral School.

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