Role

  • A Faithful Binary Circuit Model with Adversarial Noise / M Függer, J. Maier, R. Najvirt, T. Nowak, U. Schmid / Talk: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE'18), Dresden, Deutschland; 2018-03-19 - 2018-03-23; in: "Proceedings of the 2018 Design, Automation & Test in Europe (DATE)", (2018), ISBN: 978-3-9819263-1-6; 1327 - 1332
  • Measuring Metastability with Free-Running Clocks / R. Najvirt, T. Polzer, A. Steininger / Talk: 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017), San Diego, California; 2017-05-21 - 2017-05-24; in: "Proceedings 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2017)", IEEE Computer Society, 10662 Los Vaqueros Circle (2017), ISBN: 978-1-5386-2749-5; Paper ID 37, 7 pages
  • Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? / A. Steininger, R. Najvirt, J. Maier / Talk: 2016 Euromicro Conference on Digital System Design (DSD), Limassol, Portugal; 2016-08-31 - 2016-09-02; in: "2016 Euromicro Conference on Digital System Design (DSD)", IEEE, (2016), ISBN: 978-1-5090-2817-7; 372 - 379
  • The Metastable Behavior of a Schmitt-Trigger / A. Steininger, J. Maier, R. Najvirt / Talk: 22nd IEEE International Symposium on Asynchronous Circuits and Systems, Porto Alegre -- Brazil; 2016-05-08 - 2016-05-11; in: "2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)", IEEE Computer Society Conference Publishing Services (CPS), (2016), ISBN: 978-1-4673-9007-1; 57 - 64
  • On the Appropriate Handling of Metastable Voltages in FPGAs / T. Polzer, R. Najvirt, F. Beck, A. Steininger / Journal of Circuits, Systems, and Computers, 25 (2015), 3; 1640020-1 - 1640020-25
  • A Versatile and Reliable Glitch Filter for Clocks / R. Najvirt, A. Steininger / Talk: 25th International Workshop on Power and Timing Modeling, Optimization and Simulation, Salvador, Brasilien; 2015-09-01 - 2015-09-04; in: "25th International Workshop on Power and Timing Modeling, Optimization and Simulation", (2015), 8 pages
  • A Pausible Clock with Crystal Oscillator Accuracy / R. Najvirt, A. Steininger / Talk: 22nd European Conference on Circuit Theory and Design, Trondheium, Norwegen; 2015-08-24 - 2015-08-26; in: "22nd European Conference on Circuit Theory and Design", (2015), Paper ID 67, 4 pages
  • Containment of Metastable Voltages in FPGAs / R. Najvirt, T. Polzer, F. Beck, A. Steininger / Talk: 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Belgrad; 2015-04-22 - 2015-04-24; in: "18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2015), 6 pages
  • How to Synchronize a Pausible Clock to a Reference / R. Najvirt, A. Steininger / Talk: 21st IEEE International Symposium on Asynchronous Circuits and Systems, Mountain View, CA; 2015-05-04 - 2015-05-06; in: "21st IEEE International Symposium on Asynchronous Circuits and Systems", (2015), 8 pages
  • Experimental Validation of a Faithful Binary Circuit Model / R. Najvirt, M Függer, T. Nowak, U. Schmid, M. Hofbauer, K. Schweiger / Talk: Great Lakes Symposium on VLSI (GLSVLSI'15), Pittsburgh, Pennsylvania, USA; 2015; in: "Proceedings of the 25th Edition on Great Lakes Symposium on VLSI (GLSVLSI'15)", (2015), ISBN: 978-1-4503-3474-7; 355 - 360
  • Towards binary circuit models that faithfully capture physical solvability / M Függer, R. Najvirt, T. Nowak, U. Schmid / Talk: Design, Automation & Test in Europe Conference & Exhibition (DATE'15), Grenoble, France; 2015-03-09 - 2015-03-13; in: "Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE'15)", (2015), ISBN: 978-3-9815370-4-8; 1455 - 1460
  • Equivalence of Clock Gating and Synchronization with Applicability to GALS Communication / R. Najvirt, A. Steininger / Talk: 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, Isles Balears, Spain; 2014-09-29 - 2014-10-01; in: "Proceedings of the 24th International Workshop on Power and Timing Modeling, Optimization and Simulation", IEEE, (2014), ISBN: 978-1-4799-5412-4; Paper ID 29, 8 pages
  • A Generic Architecture for Robust Asynchronous Communication Links / J. Lechner, R. Najvirt / Poster: International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2012, Newcastle upon Tyne; 2012-09-04 - 2012-09-06; in: "Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation", Lecture Notes in Computer Science, 7606 (2013), ISBN: 978-3-642-36156-2; 121 - 130
  • Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs / R. Najvirt, S. Naqvi, A. Steininger / Talk: 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2013), Santa Monica, CA; 2013-05-19 - 2013-05-22; in: "Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on", (2013), ISSN: 1522-8681; 9 pages
  • A Multi-Credit Flow Control Scheme for Asynchronous NoCs / S. Naqvi, R. Najvirt, A. Steininger / Talk: 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Karoly Vary, Czech Republic; 2013-04-08 - 2013-04-10; in: "Proc. 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems", (2013), 6 pages
  • Particle Strikes in C-Gates: Relevance of SET Shapes / R. Najvirt, V. S. Veeravalli, A. Steininger / Talk: 2nd Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale, Avignon; 2013-05-30 - 2013-05-31; in: "Proceedings of the MEDIAN Workshop 2013", (2013), 4 pages
  • Description Methods for Asynchronous Circuits - A Comparison / Master Thesis by R. Najvirt / Supervisor: A. Steininger; 191-02, 2011